公开(公告)号：US20250048639A1

公开(公告)日：2025-02-06

申请号：US18653301

申请日：2024-05-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hakseon Kim ,  Kangoh Yun ,  Dongjin Lee ,  Youngrok Kim ,  Ryoongbin Lee ,  Jaeduk Lee

IPC: H10B43/40 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27

Abstract: A non-volatile memory device includes a peripheral circuit and a memory cell array that are sequentially stacked. The peripheral circuit includes, a device isolation layer defining an active region within a substrate, a first gate electrode extending in a first horizontal direction on the active region, an insulating pattern in a first recess and a second recess spaced apart in a second horizontal direction within the active region on opposing sides of the first gate electrode, a first low concentration doped region along an outer wall of the first recess, a second low concentration doped region along an outer wall of the second recess, a first source/drain region buried in the first low concentration doped region, and a second source/drain region buried in the second low concentration doped region.