公开(公告)号：US20210248475A1

公开(公告)日：2021-08-12

申请号：US17108342

申请日：2020-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngrae CHO ,  Kiseok KWON ,  Chulsoo PARK ,  Jongho KIM ,  Jaeun PARK

IPC: G06N3/08 ,  G06K9/62 ,  G06F9/345 ,  G06F9/54

Abstract: Disclosed is an electronic apparatus including a processor configured to obtain calculation information based on input data of a deconvolution calculation being input, obtain a size of output data based on the obtained calculation information, obtain a plurality of memory address values corresponding to a size of the output data using an address generation module, perform convolution calculation based on the calculation information using a convolution calculation module to obtain an intermediate value in the convolution calculation process, obtain a memory address value corresponding to the obtained intermediate value of the plurality of obtained memory addresses using the address generation module, store the obtained intermediate value in the memory address value corresponding to the intermediate value, accumulate at least one intermediate value based on the memory address value corresponding to the intermediate value using a cumulative calculation module, and obtain a deconvolution calculation value with respect to the input data based on the accumulated at least one intermediate value.

公开(公告)号：US20240412052A1

公开(公告)日：2024-12-12

申请号：US18811302

申请日：2024-08-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Meejeong PARK ,  Jihun OH ,  Youngrae CHO ,  Jonghun LEE

IPC: G06N3/0495 ,  G06N3/0464

Abstract: A data processing method for neural network quantization, includes: obtaining a quantized weight by quantizing a weight of a neural network; obtaining a quantization error that is a difference between the weight and the quantized weight; obtaining input data with respect to the neural network; obtaining a first convolution result by performing convolution on the quantized weight and the input data; obtaining a second convolution result by performing convolution on the quantization error and the input data; obtaining a scaled second convolution result by scaling the second convolution result based on bit shifting; and obtaining output data by using the first convolution result and the scaled second convolution result.

公开(公告)号：US20230214445A1

公开(公告)日：2023-07-06

申请号：US18120241

申请日：2023-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulsoo PARK ,  Jongho KIM ,  Youngrae CHO ,  Kiseok KWON ,  Jonghun LEE

IPC: G06F17/15 ,  G06F17/16

CPC classification number: G06F17/153 ,  G06F17/16

Abstract: A memory of an electronic device stores three-dimensional input data comprising (i) input values, (ii) first kernel information, and (iii) second kernel information. The processor includes multiplication modules corresponding to the channels and performs a convolution operation based on the input values and the weights through the multiplication modules. Based on a depthwise convolution operation, a processor of the electronic device controls an input selection module to (a) configure the input values to correspond to a first channel among the channels and (b) input the input values to two or more multiplication modules among the multiplication modules. The processor inputs weights, obtains intermediate values, and obtains output values based on each of a summed result by summing intermediate values respectively corresponding to locations of the kernels from among the intermediate values through a first intermediate value accumulation module.