公开(公告)号：US20210248475A1

公开(公告)日：2021-08-12

申请号：US17108342

申请日：2020-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngrae CHO ,  Kiseok KWON ,  Chulsoo PARK ,  Jongho KIM ,  Jaeun PARK

IPC: G06N3/08 ,  G06K9/62 ,  G06F9/345 ,  G06F9/54

Abstract: Disclosed is an electronic apparatus including a processor configured to obtain calculation information based on input data of a deconvolution calculation being input, obtain a size of output data based on the obtained calculation information, obtain a plurality of memory address values corresponding to a size of the output data using an address generation module, perform convolution calculation based on the calculation information using a convolution calculation module to obtain an intermediate value in the convolution calculation process, obtain a memory address value corresponding to the obtained intermediate value of the plurality of obtained memory addresses using the address generation module, store the obtained intermediate value in the memory address value corresponding to the intermediate value, accumulate at least one intermediate value based on the memory address value corresponding to the intermediate value using a cumulative calculation module, and obtain a deconvolution calculation value with respect to the input data based on the accumulated at least one intermediate value.

公开(公告)号：US20220312613A1

公开(公告)日：2022-09-29

申请号：US17701064

申请日：2022-03-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongsu LEE ,  Yoonhee LEE ,  Kiseok KWON ,  Sungho CHO

IPC: H05K5/04 ,  H04B1/3888 ,  C25D11/12 ,  C25D21/12

Abstract: An electronic device is provided. The electronic device includes a housing that forms a portion of an outer surface of the electronic device and a display disposed in the housing and visually exposed through one side of the housing. The housing includes a first portion containing a metallic material, and the first portion includes a base material layer made of the metallic material, a first film layer that is disposed adjacent to a surface of the housing and that contains oxide of the metallic material, and a second film layer that is disposed between the base material layer and the first film layer and that contains oxide of the metallic material. The first film layer includes a first pore structure that extends in a direction substantially perpendicular to a surface of the first film layer, and the second film layer includes a second pore structure that is at least partially in fluid communication with the first pore structure and that extends in a radial shape toward the base material layer.

公开(公告)号：US20230214445A1

公开(公告)日：2023-07-06

申请号：US18120241

申请日：2023-03-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chulsoo PARK ,  Jongho KIM ,  Youngrae CHO ,  Kiseok KWON ,  Jonghun LEE

IPC: G06F17/15 ,  G06F17/16

CPC classification number: G06F17/153 ,  G06F17/16

Abstract: A memory of an electronic device stores three-dimensional input data comprising (i) input values, (ii) first kernel information, and (iii) second kernel information. The processor includes multiplication modules corresponding to the channels and performs a convolution operation based on the input values and the weights through the multiplication modules. Based on a depthwise convolution operation, a processor of the electronic device controls an input selection module to (a) configure the input values to correspond to a first channel among the channels and (b) input the input values to two or more multiplication modules among the multiplication modules. The processor inputs weights, obtains intermediate values, and obtains output values based on each of a summed result by summing intermediate values respectively corresponding to locations of the kernels from among the intermediate values through a first intermediate value accumulation module.

公开(公告)号：US20210365779A1

公开(公告)日：2021-11-25

申请号：US17171290

申请日：2021-02-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jihun OH ,  Sangjeong LEE ,  Meejeong PARK ,  Gaurav POONIWALA ,  Kiseok KWON

IPC: G06N3/08 ,  G06N3/063 ,  G06N3/04

Abstract: An electronic apparatus is provided. The electronic apparatus includes a memory configured to store an artificial intelligence (AI) model including a plurality of layers and a processor, and the AI model may include a plurality of weight values that are scaled based on shift scaling factors different by a plurality of channels included in each of the plurality of layers and quantized by the plurality of layers, and the processor may, based on receiving input data, in a neural network computation process for the input data, compute a channel-wise computation result with an inverse-scaled composite scale parameter based on a shift scaling factor corresponding to each channel.