公开(公告)号：US10886277B2

公开(公告)日：2021-01-05

申请号：US16106087

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo Hong ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US11574912B2

公开(公告)日：2023-02-07

申请号：US17112195

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo Hong ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US10553449B2

公开(公告)日：2020-02-04

申请号：US15700491

申请日：2017-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sun-Hye Hwang ,  Youn-Joung Cho ,  Won-Woong Chung ,  Nam-Gun Kim ,  Kong-Soo Lee ,  Badro Im ,  Yoon-Chul Cho

IPC: H01L21/3213 ,  H01L21/311

Abstract: A method of forming a pattern includes forming an etch target layer on a substrate, forming sacrificial patterns on the etch target layer, the sacrificial patterns including a carbon-containing material, providing a silicon-sulfur compound or a sulfur-containing gas onto the sacrificial patterns to form a seed layer, providing a silicon precursor onto the seed layer to form silicon-containing mask patterns, and at least partially etching the etch target layer using the mask patterns.

公开(公告)号：US20190139963A1

公开(公告)日：2019-05-09

申请号：US16106087

申请日：2018-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo HONG ,  Young-Ju Lee ,  Joon-Yong Choe ,  Jung-Hyun Kim ,  Sang-Jun Lee ,  Hyeon-Kyu Lee ,  Yoon-Chul Cho ,  Je-Min Park ,  Hyo-Dong Ban

IPC: H01L27/108 ,  H01L23/535 ,  H01L21/768

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.