ECC DECODER AND MEMORY CONTROLLER INCLUDING THE SAME

    公开(公告)号:US20240143442A1

    公开(公告)日:2024-05-02

    申请号:US18495156

    申请日:2023-10-26

    CPC classification number: G06F11/1068 G06F11/0772 G06F11/1048

    Abstract: A memory controller includes a processor, which is configured to determine one of a first operation mode and a second operation mode as an operation mode based on a lifespan or retention of a memory device. The processor is configured to transmit to the memory device, a read command for obtaining hard decision (HD) data and a first piece of SD data during a time period of a single read, or a read command for obtaining a second piece of SD data from a plurality of reads. A decoding circuit is configured to perform iterative decoding based on the first piece of SD data or the second piece of SD data. The first operation mode is for sequentially transmitting the coarse SD read command and the fine SD read command to the memory device, whereas the second operation mode is for transmitting the fine SD read command.

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