公开(公告)号：US20240103735A1

公开(公告)日：2024-03-28

申请号：US18333690

申请日：2023-06-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungjun Shin ,  Yeongwoo Kang ,  DongHyeok Cho ,  Younghun Seo

IPC: G06F3/06

CPC classification number: G06F3/0614 ,  G06F3/0659 ,  G06F3/0673

Abstract: Disclosed is a memory device which includes a first memory cell that is electrically connected with a first word line and a first bit line, a first bit line sense amplifier circuit that is electrically connected with the first bit line, a first local sense amplifier circuit that is electrically connected with the first bit line sense amplifier circuit through a first local input/output line, a first local driver that is electrically connected with the first local sense amplifier circuit through a first pre-global input/output line, and a sense amplifier and write driver that is electrically connected with the first local driver through a global input/output line, and the first local driver selectively electrical-disconnects the first pre-global input/output line from the global input/output line, based on an operation for the first memory cell.

公开(公告)号：US20250124969A1

公开(公告)日：2025-04-17

申请号：US18669633

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Yeongwoo Kang ,  Yongjun Kim

IPC: G11C11/4091 ,  G11C11/408

Abstract: Memory devices and methods of operating thereof. A memory device may include a plurality of memory cells each including a cell transistor having a back gate that is shared with a cell transistor of an adjacent memory cell through a back gate line, a forward gate that is connected to a corresponding word line, and a cell capacitor that is connected to a first electrode of the cell transistor; a sub-word line driver configured to apply a word line driving voltage to a selected word line; a back gate driver configured to change a back gate voltage applied to the back gate line from a first voltage level to a second voltage level during an active period in which the selected word line is enabled; and a sense amplifier configured to sense data through bit lines connected to second electrodes of the cell transistors of the plurality of memory cells.

公开(公告)号：US20250056795A1

公开(公告)日：2025-02-13

申请号：US18441968

申请日：2024-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyoung Lee ,  Hyun-Chul Yoon ,  Yeongwoo Kang

IPC: H10B20/00 ,  G11C29/04 ,  H10B12/00 ,  H10B20/25

Abstract: The present disclosure relates to memory devices. An example memory device includes a memory cell region including a memory cell array is configured to store data, and an antifuse cell array including a plurality of antifuse bit lines, a plurality of antifuse word lines, and a plurality of program transistors that is electrically coupled to a first antifuse bit line among the plurality of antifuse bit lines and that are coupled in parallel with one another. The memory device includes a peripheral circuit region including an antifuse sense amplifier is configured to output one-time programmable (OTP) data stored in the plurality of program transistors.