公开(公告)号：US20230281128A1

公开(公告)日：2023-09-07

申请号：US17834896

申请日：2022-06-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wenqin HUANGFU ,  Krishna T. MALLADI ,  Andrew CHANG

IPC: G06F12/0817 ,  G06F12/0831 ,  G06F9/52

CPC classification number: G06F12/0828 ,  G06F12/0831 ,  G06F9/52

Abstract: A memory system is disclosed. The memory system may include a first cache-coherent interconnect memory module and a second cache-coherent interconnect memory module. A cache-coherent interconnect switch may connect the first cache-coherent interconnect memory module, the second cache-coherent interconnect memory module, and a processor. A processing element may process a data stored on at least one of the first cache-coherent interconnect memory module and the second cache-coherent interconnect memory module.

公开(公告)号：US20210349837A1

公开(公告)日：2021-11-11

申请号：US17214778

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wenqin HUANGFU ,  Krishna T. MALLADI ,  Dongyan JIANG

IPC: G06F12/14 ,  G06F13/42 ,  G06F13/16 ,  G06F9/50

Abstract: A memory module may include one or more memory devices, and a near-memory computing module coupled to the one or more memory devices, the near-memory computing module including one or more processing elements configured to process data from the one or more memory devices, and a memory controller configured to coordinate access of the one or more memory devices from a host and the one or more processing elements. A method of processing a dataset may include distributing a first portion of the dataset to a first memory module, distributing a second portion of the dataset to a second memory module, constructing a first local data structure at the first memory module based on the first portion of the dataset, constructing a second local data structure at the second memory module based on the second portion of the dataset, and merging the first and second local data structures.