HBM WITH IN-MEMORY CACHE MANAGER
    1.
    发明申请

    公开(公告)号:US20180032437A1

    公开(公告)日:2018-02-01

    申请号:US15272339

    申请日:2016-09-21

    Abstract: A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.

    HBM with in-memory cache manager
    2.
    发明授权

    公开(公告)号:US10180906B2

    公开(公告)日:2019-01-15

    申请号:US15272339

    申请日:2016-09-21

    Abstract: A system and method for using high bandwidth memory as cache memory. A high bandwidth memory may include a logic die, and, stacked on the logic die, a plurality of dynamic read-only memory dies. The logic die may include a cache manager, that may interface to external systems through an external interface conforming to the JESD235A standard, and that may include an address translator, a command translator, and a tag comparator. The address translator may translate each physical address received through the external interface into a tag value, a tag address in the stack of memory dies, and a data address in the stack of memory dies. The tag comparator may determine whether a cache hit or cache miss has occurred, according to whether the tag value generated by the address translator matches the tag value stored at the tag address.

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