公开(公告)号：US20180033637A1

公开(公告)日：2018-02-01

申请号：US15443370

申请日：2017-02-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun KIM ,  Sangmin LEE ,  Sinhae DO ,  Seok-Won CHO ,  Taeseop CHOI ,  Kon HA

IPC: H01L21/311 ,  H01L21/033 ,  G03F7/20 ,  H01L21/308

CPC classification number: H01L21/31116 ,  G03F7/70033 ,  H01L21/0332 ,  H01L21/3081 ,  H01L21/31144 ,  H01L27/10894

Abstract: Example embodiments relate to a method for fabricating a semiconductor device. The method for fabricating a semiconductor device includes stacking on a substrate an etching target layer, a first mask layer, and a photoresist layer, irradiating extreme ultraviolet (EUV) radiation on the photoresist layer to form a photoresist pattern, patterning the first mask layer to form a first mask pattern using the photoresist pattern as an etching mask, and patterning the etching target layer to form a target pattern using the first mask pattern as an etching mask. The first mask layer includes at least one of a silicon layer and a titanium oxide layer.

公开(公告)号：US20190287975A1

公开(公告)日：2019-09-19

申请号：US16422054

申请日：2019-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun KIM ,  Joonkyu RHEE ,  Ji-Hye Lee ,  Chanmi LEE ,  Taeseop CHOI

IPC: H01L27/108

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.

公开(公告)号：US20170271340A1

公开(公告)日：2017-09-21

申请号：US15405808

申请日：2017-01-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam-Gun KIM ,  Joonkyu RHEE ,  Ji-Hye LEE ,  Chanmi LEE ,  Taeseop CHOI

IPC: H01L27/108 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L27/10814 ,  H01L21/7682 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888

Abstract: Example embodiments relate to a semiconductor device. The semiconductor device includes a substrate including an active region extending in a first direction, a plurality of bit lines running across the active region in a second direction crossing the first direction, a first spacer on a sidewall of the bit line, and a storage node contact on the active region between adjacent bit lines. The first spacer includes a first part between the storage node contact and the bit line, a second part between the first part and the storage node contact, and a third part between the first and second parts. A minimum vertical thickness of the first part is greater than a maximum vertical thickness of the third part. The maximum vertical thickness of the third part is greater than a maximum vertical thickness of the second part.