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公开(公告)号:US20240250066A1
公开(公告)日:2024-07-25
申请号:US18535339
申请日:2023-12-11
Applicant: Samsung Electronics Co., Ltd.
Inventor: Joonghyun BAEK , Hyungu KANG , Cheol-Woo LEE , Sunghwan YOON , Eunjeong IM
IPC: H01L25/065 , H01L23/00 , H01L23/31 , H01L23/538 , H01L25/10
CPC classification number: H01L25/0652 , H01L23/3128 , H01L23/5381 , H01L24/32 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32145 , H01L2224/32225 , H01L2224/48145 , H01L2224/48227 , H01L2224/73215 , H01L2225/06506 , H01L2225/0651 , H01L2225/06562
Abstract: A semiconductor package including first and second chip stacks each including semiconductor chips having an offset stack structure, the second chip stack horizontally spaced apart from the first chip stack, a first buffer chip on the substrate and at a side of the first chip stack, a second buffer chip on the substrate and at a side of the second chip stack, a connection substrate on the first and second chip stacks, a first mold layer covering the substrate, the first chip stack, and the second stack and exposing a top surface of the connection substrate, third and fourth chip stacks each including semiconductor chips having an offset stack structure on the first mold layer and, the fourth chip stack horizontally spaced apart from the third chip stack, and a second mold layer covering the first mold layer, the third chip stack, and the fourth chip stack may be provided.
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公开(公告)号:US20240114641A1
公开(公告)日:2024-04-04
申请号:US18516224
申请日:2023-11-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Byounghee CHOI , Giwon SEOL , Sunghwan YOON , Kangeun LEE , Jinho LEE , Doohyeon CHO , Youngsoo HA
CPC classification number: H05K5/04 , C25D11/08 , C25D11/12 , C25D11/246
Abstract: A housing of an electronic device is disclosed. A housing of an electronic device according to various embodiments of the disclosure may include: a base material containing an aluminum alloy material; a barrier layer formed by anodizing the aluminum of the base material on a surface facing a first direction of the base material, the barrier layer having a thickness of 50 to 150 nanometers; a first porous film located in the first direction with respect to the barrier layer; and a second porous film formed between the first porous film and the barrier layer.
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