公开(公告)号：US10910231B2

公开(公告)日：2021-02-02

申请号：US16453481

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo Chung ,  Kyoung Ha Eom ,  Hyunchul Lee ,  Sounghee Lee ,  Jiseung Lee

IPC: H01L21/311 ,  H01L21/308

Abstract: A method of fabricating a semiconductor device includes forming a first etching pattern structure and a second etching pattern structure on a substrate. The first cell etching pattern structure has a top surface at a level that is different from that of a top surface of the second etching pattern structure. The method further includes forming a first spacer layer on the first etching pattern structure and the second etching pattern structure. The first spacer layer covers top and lateral surfaces of the first etching pattern structure and top and lateral surfaces of the second etching pattern structure. The method further includes performing a first etching process on the first spacer layer to form a first spacer and a second spacer. The first spacer layer is fully exposed during the first etching process of the first spacer layer.

公开(公告)号：US20190214273A1

公开(公告)日：2019-07-11

申请号：US16132895

申请日：2018-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Yunseung Kang ,  Sounghee Lee ,  Jiseung Lee ,  Sanggyo Chung

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

Abstract: Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.

公开(公告)号：US10522366B2

公开(公告)日：2019-12-31

申请号：US16132895

申请日：2018-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Yunseung Kang ,  Sounghee Lee ,  Jiseung Lee ,  Sanggyo Chung

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.