公开(公告)号：US20190214273A1

公开(公告)日：2019-07-11

申请号：US16132895

申请日：2018-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Yunseung Kang ,  Sounghee Lee ,  Jiseung Lee ,  Sanggyo Chung

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

Abstract: Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.

公开(公告)号：US12293921B2

公开(公告)日：2025-05-06

申请号：US18497172

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo Chung ,  Jiseung Lee ,  Kyoungha Eom ,  Hyunchul Lee

IPC: H01L21/308 ,  C23C16/40 ,  C23C16/455 ,  C23C16/56 ,  H01L21/3065 ,  H10B12/00

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

公开(公告)号：US20210217625A1

公开(公告)日：2021-07-15

申请号：US17022208

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggyo Chung ,  Jiseung Lee ,  Kyoungha Eom ,  Hyunchul Lee

IPC: H01L21/308 ,  C23C16/455 ,  C23C16/56 ,  C23C16/40 ,  H01L21/3065 ,  H01L27/108

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

公开(公告)号：US11842899B2

公开(公告)日：2023-12-12

申请号：US17022208

申请日：2020-09-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanggyo Chung ,  Jiseung Lee ,  Kyoungha Eom ,  Hyunchul Lee

IPC: H01L21/308 ,  C23C16/455 ,  C23C16/56 ,  C23C16/40 ,  H01L21/3065 ,  H10B12/00

CPC classification number: H01L21/3088 ,  C23C16/401 ,  C23C16/45525 ,  C23C16/56 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3085 ,  H01L21/3086 ,  H10B12/0335 ,  H10B12/053 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

公开(公告)号：US10910231B2

公开(公告)日：2021-02-02

申请号：US16453481

申请日：2019-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo Chung ,  Kyoung Ha Eom ,  Hyunchul Lee ,  Sounghee Lee ,  Jiseung Lee

IPC: H01L21/311 ,  H01L21/308

Abstract: A method of fabricating a semiconductor device includes forming a first etching pattern structure and a second etching pattern structure on a substrate. The first cell etching pattern structure has a top surface at a level that is different from that of a top surface of the second etching pattern structure. The method further includes forming a first spacer layer on the first etching pattern structure and the second etching pattern structure. The first spacer layer covers top and lateral surfaces of the first etching pattern structure and top and lateral surfaces of the second etching pattern structure. The method further includes performing a first etching process on the first spacer layer to form a first spacer and a second spacer. The first spacer layer is fully exposed during the first etching process of the first spacer layer.

公开(公告)号：US20240063024A1

公开(公告)日：2024-02-22

申请号：US18497172

申请日：2023-10-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanggyo Chung ,  Jiseung Lee ,  Kyoungha Eom ,  Hyunchul Lee

IPC: H01L21/308 ,  C23C16/455 ,  C23C16/56 ,  C23C16/40 ,  H01L21/3065 ,  H10B12/00

CPC classification number: H01L21/3088 ,  C23C16/45525 ,  C23C16/56 ,  C23C16/401 ,  H01L21/3065 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/3085 ,  H10B12/34 ,  H10B12/053 ,  H10B12/315 ,  H10B12/0335 ,  H10B12/482

Abstract: In a method of cutting a fine pattern, a line structure is formed on a substrate. The line structure extends in a first direction, and includes a pattern and a first mask. The pattern and the first mask include different materials. A sacrificial layer is formed on the substrate to cover the line structure. The sacrificial layer is partially etched to form a first opening partially overlapping the line structure in a vertical direction. A portion of the first mask, an upper portion of the pattern and/or a portion of the sacrificial layer under the first opening are partially etched using an etching gas having no etching selectivity among the pattern, the first mask and the sacrificial layer. A lower portion of the pattern under the upper portion thereof is removed to divide the pattern into a plurality of pieces spaced apart from each other in the first direction.

公开(公告)号：US10522366B2

公开(公告)日：2019-12-31

申请号：US16132895

申请日：2018-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunchul Lee ,  Yunseung Kang ,  Sounghee Lee ,  Jiseung Lee ,  Sanggyo Chung

IPC: H01L21/3213 ,  H01L21/033 ,  H01L21/308 ,  H01L21/311

Abstract: Disclosed is a method of fabricating a semiconductor device. The method includes forming a lower layer on a substrate, forming on the lower layer a sacrificial layer and an etching pattern, forming a first spacer layer on the sacrificial layer and the etching pattern, etching the sacrificial layer and the first spacer layer to form a sacrificial pattern and a first spacer on at least a portion of a top surface of the sacrificial pattern, forming a second spacer layer on the sacrificial pattern and the first spacer, etching the second spacer layer and the first spacer to form a second spacer on a sidewall of the sacrificial pattern, and partially etching the lower layer to form a pattern. The second spacer is used as an etching mask to partially etch the lower layer.

公开(公告)号：US09159729B2

公开(公告)日：2015-10-13

申请号：US14028976

申请日：2013-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyongsoo Kim ,  Jin-Su Lee ,  Hojun Kwon ,  Dongkyun Park ,  Jiseung Lee ,  Young-Seok Choi

IPC: H01L27/108 ,  H01L49/02

CPC classification number: H01L27/10817 ,  H01L27/10852 ,  H01L28/40 ,  H01L28/91

Abstract: Capacitor of a semiconductor device, and a method of fabricating the same, include sequentially forming a mold structure and a polysilicon pattern over a semiconductor substrate, patterning the mold structure using the polysilicon pattern as an etch mask to form lower electrode holes penetrating the mold structure, forming a protection layer covering a surface of the polysilicon pattern, forming lower electrodes in the lower electrode holes provided with the protection layer, removing the polysilicon pattern and the protection layer to expose upper sidewalls of the lower electrodes, removing the mold structure to expose lower sidewalls of the lower electrodes, and sequentially forming a dielectric and an upper electrode covering the lower electrodes.

Abstract translation: 半导体器件的电容器及其制造方法包括在半导体衬底上顺序地形成模具结构和多晶硅图案，使用多晶硅图案将模具结构图案化为蚀刻掩模，以形成贯穿模具结构的下部电极孔 形成覆盖多晶硅图案的表面的保护层，在设置有保护层的下电极孔中形成下电极，去除多晶硅图案和保护层以暴露下电极的上侧壁，去除模具结构暴露 下电极的下侧壁，并且依次形成覆盖下电极的电介质和上电极。