公开(公告)号：US09864720B2

公开(公告)日：2018-01-09

申请号：US15264946

申请日：2016-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan Yeob Chae ,  Hyun-Hyuck Kim ,  Sang Hune Park ,  Shin Young Yi ,  Won Lee

IPC: G11C7/00 ,  G06F13/42 ,  G11C7/22

CPC classification number: G06F13/4243 ,  G11C7/22

Abstract: A data processing circuit includes a delay circuit configured to delay a data signal and generate delayed data signals each having a different delay; and an output control circuit configured to output a first data signal among the delayed data signals as a data signal sampled at a first edge of a sampling clock signal, and output a second data signal among the delayed data signals as a data signal sampled at a second edge of the sampling clock signal.