Abstract:
An integrated circuit memory device includes a substrate having a sense amplifier region or a word line driver region comprising circuits configured to operate a memory cell array. The substrate further includes a conjunction region adjacent the sense amplifier region or word line driver region and defining a boundary therebetween. A plurality of gate patterns extends on the substrate. The gate patterns include peripheral gate patterns extending in the sense amplifier region or word line driver region, and conjunction gate patterns extending in the conjunction region. Ones of the conjunction gate patterns and ones of the peripheral gate patterns proximate the boundary extend substantially parallel along the boundary between the conjunction region and the sense amplifier region or word line driver region.