Integrated Circuit Memory Devices Including Parallel Patterns in Adjacent Regions
    1.
    发明申请
    Integrated Circuit Memory Devices Including Parallel Patterns in Adjacent Regions 审中-公开
    在相邻区域包括并行模式的集成电路存储器件

    公开(公告)号:US20140246725A1

    公开(公告)日:2014-09-04

    申请号:US14196512

    申请日:2014-03-04

    CPC classification number: H01L27/10897 G11C11/4097 H01L27/0207

    Abstract: An integrated circuit memory device includes a substrate having a sense amplifier region or a word line driver region comprising circuits configured to operate a memory cell array. The substrate further includes a conjunction region adjacent the sense amplifier region or word line driver region and defining a boundary therebetween. A plurality of gate patterns extends on the substrate. The gate patterns include peripheral gate patterns extending in the sense amplifier region or word line driver region, and conjunction gate patterns extending in the conjunction region. Ones of the conjunction gate patterns and ones of the peripheral gate patterns proximate the boundary extend substantially parallel along the boundary between the conjunction region and the sense amplifier region or word line driver region.

    Abstract translation: 集成电路存储器件包括具有读出放大器区域或字线驱动器区域的衬底,该区域包括被配置为操作存储器单元阵列的电路。 衬底还包括与感测放大器区域或字线驱动器区域相邻并在其间限定边界的连接区域。 多个栅极图案在基板上延伸。 栅极图案包括在读出放大器区域或字线驱动器区域中延伸的外围栅极图案,以及在连接区域中延伸的连接栅极图案。 连接栅极图案和靠近边界的外围栅极图案的一个沿着连接区域和读出放大器区域或字线驱动器区域之间的边界基本上平行延伸。

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