公开(公告)号：US12250709B2

公开(公告)日：2025-03-11

申请号：US17750981

申请日：2022-05-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Balgeum Choe ,  Chanhong Kim ,  Seunghui Hong ,  Hyunjong Na ,  Hyungju Nam ,  Changkee Min ,  Hanjun Park ,  Heenam Cho

IPC: H04W72/542 ,  H04B7/08 ,  H04B17/336 ,  H04L1/00 ,  H04L1/20 ,  H04L5/00 ,  H04L25/02 ,  H04W52/14 ,  H04W52/36 ,  H04W72/04

Abstract: An electronic device and a method are provided. The electronic device includes communication circuitry configured to receive signals from at least one user equipment (UE), and a processor, wherein the processor may be configured to determine a reception quality of a signal obtained through the communication circuitry, obtain an offset corresponding to a channel characteristic of the signal, determine, based on the offset indicating a signal quality difference corresponding to a difference between a reception dimension (Rx dimension) at signal reception and a target Rx dimension and the reception quality, an expected reception quality corresponding to the target Rx dimension, pre-schedule the target Rx dimension and a frequency resource to the at least one UE, determine an expected throughput for the at least one UE based on the expected reception quality, determine the target Rx dimension, and receive or transmit data from or to the UE.

公开(公告)号：US12199044B2

公开(公告)日：2025-01-14

申请号：US17714412

申请日：2022-04-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghui Hong ,  Sangwon Kim ,  Jeeyong Kim ,  Subin Shin ,  Habin Lim

IPC: H10B43/27 ,  H01L23/535 ,  H10B41/27 ,  H10B41/41 ,  H10B43/40

Abstract: A peripheral circuit structure may include peripheral circuits and peripheral circuit lines on a semiconductor substrate, a semiconductor layer including cell array and connection regions on the peripheral circuit structure, a stack including electrodes stacked on the semiconductor layer having a stepwise structure on the connection region, and a planarization insulating layer covering the stack, vertical structures on the cell array region penetrating the stack, including a data storage pattern, a dam group including insulating dams on the connection region penetrating the stack, penetration plugs penetrating the insulating dams and connected to respective peripheral circuit lines, the dam group including a first insulating dam farthest from the cell array region, the first insulating dam including first and second sidewall portions spaced apart, a difference between upper and lower thicknesses of the second sidewall portion of the first insulating dam is larger than that of the first sidewall portion.