公开(公告)号：US20240170455A1

公开(公告)日：2024-05-23

申请号：US18226529

申请日：2023-07-26

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Yonghoe CHO ,  Seunghoon YEON ,  SeungRyong OH

IPC分类号： H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L23/3107 ,  H01L24/08 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/08148 ,  H01L2224/16148 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06544 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438

摘要： A semiconductor package is provided that includes: a first semiconductor die, and a second semiconductor die on the first semiconductor die. The first semiconductor die includes a semiconductor substrate, a wiring layer on an active surface of the semiconductor substrate, a redistribution pattern on an inactive surface of the semiconductor substrate, a first passivation layer on the inactive surface of the semiconductor substrate wherein the first passivation layer is on the redistribution pattern and has an opening that exposes a top surface of the redistribution pattern, and a backside pad on the first passivation layer and coupled through the opening to the redistribution pattern. An inner lateral surface of the opening is inclined at an angle of 90 to 105 degrees relative to the top surface of the redistribution pattern. A thickness of the first passivation layer is 0.3 to 0.5 times a thickness of the redistribution pattern.

公开(公告)号：US20240096841A1

公开(公告)日：2024-03-21

申请号：US18456261

申请日：2023-08-25

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Ohguk KWON ,  Sunjae KIM ,  Seunghoon YEON ,  Seungryong OH ,  Huiyeong JANG

IPC分类号： H01L23/00 ,  H01L21/66 ,  H01L25/065

CPC分类号： H01L24/32 ,  H01L22/32 ,  H01L24/16 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16148 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/26145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/3841

摘要： A semiconductor package includes a first semiconductor chip including a first substrate, a plurality of through electrodes penetrating the first substrate, and first bonding pads provided on one surface of the first substrate and electrically connected to the plurality of through electrodes, a second semiconductor chip including a second substrate, a second wiring layer provided on one surface of the second substrate and having redistribution pads and test pads, and second bonding pads on the redistribution pads, the second semiconductor chip being stacked on the first semiconductor chip via conductive bumps that are disposed between first and second bonding pads, an adhesive layer filling a space between the conductive bumps, and flow prevention structures in the adhesive layer on a test pad region where the test pads are disposed.

公开(公告)号：US20230117072A1

公开(公告)日：2023-04-20

申请号：US18066487

申请日：2022-12-15

申请人： Samsung Electronics Co., Ltd.

发明人： Chajea JO ,  Ohguk KWON ,  Namhoon KIM ,  Hyoeun KIM ,  Seunghoon YEON

IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

摘要： An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US20210407890A1

公开(公告)日：2021-12-30

申请号：US17162418

申请日：2021-01-29

申请人： Samsung Electronics Co., Ltd.

发明人： Chajea JO ,  Ohguk KWON ,  Namhoon KIM ,  Hyoeun KIM ,  Seunghoon YEON

IPC分类号： H01L23/48 ,  H01L25/065 ,  H01L23/00 ,  H01L21/768

摘要： An integrated circuit device includes a semiconductor substrate, first through-silicon-via (TSV) structures penetrating a first region of the semiconductor substrate and spaced apart from each other by a first pitch, a first individual device between the first TSV structures and spaced apart from the first TSV structures by a distance that is greater than a first keep-off distance, and second TSV structures penetrating a second region of the semiconductor substrate and spaced apart from each other by a second pitch that is less than the first pitch. The second region of the semiconductor device does not include an individual device that is homogeneous with the first individual device and between the second TSV structures.

公开(公告)号：US20220262689A1

公开(公告)日：2022-08-18

申请号：US17733411

申请日：2022-04-29

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hyoeun KIM ,  Yonghoe CHO ,  Sunkyoung SEO ,  Seunghoon YEON ,  Sanguk HAN

IPC分类号： H01L21/66 ,  H01L25/065 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00 ,  G01R31/28 ,  G01R27/26

摘要： A chip-stacked semiconductor package includes a first chip including a first detection pad and a second detection pad; a second chip provided on the first chip, the second chip including a third detection pad facing the first detection pad and a fourth detection pad facing the second detection pad; and a first medium provided between the first detection pad and the third detection pad to connect the first detection pad to the third detection pad through the first medium, and a second medium, different from the first medium, provided between the second detection pad and the fourth detection pad to connect the second detection pad to the fourth detection pad through the second medium.

公开(公告)号：US20190214359A1

公开(公告)日：2019-07-11

申请号：US16044696

申请日：2018-07-25

申请人： Samsung Electronics Co., Ltd.

发明人： Seunghoon YEON ,  Hyoeun KIM ,  Jongbo SHIM ,  Yonghoe CHO

IPC分类号： H01L23/00 ,  H01L23/528 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56

摘要： A semiconductor package may include a base layer, and a redistribution layer on the base layer. The semiconductor package may include a first pattern, a second pattern, and a passivation layer covering the first and second patterns. The semiconductor package may include a semiconductor chip on the base layer, a first connection terminal between the base layer and the semiconductor chip and coupled to one of chip pads of the semiconductor chip, and a mold layer between the base layer and the semiconductor chip. The first connection terminal may extend into the passivation layer and may be coupled to the first pattern. The second pattern may be electrically insulated from the semiconductor chip.