公开(公告)号：US20140149808A1

公开(公告)日：2014-05-29

申请号：US14054957

申请日：2013-10-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-Young SEO ,  Chul-Woo PARK

IPC: G06F11/07

CPC classification number: G06F11/073 ,  G06F11/076 ,  G11C7/1006 ,  G11C7/1063

Abstract: In one example embodiment, a memory device includes a cell array configured to receive data at an associated address in response to a write command. The memory device further includes a storage unit configured to receive the associated address and the data in response to the write command and output the data to the associated address of the cell array in response to a rewrite command. The memory device further includes a violation determining unit configured to determine violation data, count a number of the violation data and determine data written to the storage unit as the violation data if a storage duration of the written data is less than a write recovery time (tWR).

Abstract translation: 在一个示例实施例中，存储器设备包括被配置为响应于写入命令在相关联的地址处接收数据的单元阵列。 存储装置还包括存储单元，其被配置为响应于写入命令接收相关联的地址和数据，并且响应于重写命令将数据输出到单元阵列的相关联的地址。 所述存储装置还包括违规判定部，其被配置为如果写入数据的存储持续时间小于写恢复时间，则确定违规数据，对违反数据的数量进行计数，并将写入所述存储单元的数据确定为所述违规数据 tWR）。