公开(公告)号：US10284198B2

公开(公告)日：2019-05-07

申请号：US15282291

申请日：2016-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yeol Lee ,  Seokil Kim ,  Hoiju Chung ,  Yongjae Shin ,  YouKeun Han

IPC: H03K19/00 ,  G11C7/10

Abstract: A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration circuits therein. The memory controller, which is electrically coupled to the memory module, includes a ZQ global managing circuit therein. This ZQ global managing circuit is configured to determine a plurality of calibration values associated the corresponding ZQ calibration circuits in the plurality of memory devices, in response to calibration result data generated by the plurality of ZQ calibration circuits. The memory module is mounted within a memory slot. In addition, the plurality of calibration values account for signal loading characteristics of the memory module within the memory slot.

公开(公告)号：US09812220B2

公开(公告)日：2017-11-07

申请号：US15207557

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC: G11C7/10 ,  G11C29/34 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/4076 ,  G11C11/4093 ,  G11C5/04

CPC classification number: G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

Abstract: A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

公开(公告)号：US20170099050A1

公开(公告)日：2017-04-06

申请号：US15282291

申请日：2016-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Yeol Lee ,  Seokil Kim ,  Hoiju Chung ,  Yongjae Shin ,  YouKeun Han

IPC: H03K19/00 ,  G11C7/10

CPC classification number: H03K19/0005 ,  G11C7/1057 ,  G11C2207/2254

Abstract: A memory system includes a memory module and a memory controller. The memory module includes a plurality of memory devices with corresponding ZQ calibration circuits therein. The memory controller, which is electrically coupled to the memory module, includes a ZQ global managing circuit therein. This ZQ global managing circuit is configured to determine a plurality of calibration values associated the corresponding ZQ calibration circuits in the plurality of memory devices, in response to calibration result data generated by the plurality of ZQ calibration circuits. The memory module is mounted within a memory slot. In addition, the plurality of calibration values account for signal loading characteristics of the memory module within the memory slot.

公开(公告)号：US09922724B2

公开(公告)日：2018-03-20

申请号：US15713936

申请日：2017-09-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC: G11C7/10 ,  G11C29/34 ,  G06F3/06 ,  G06F12/1009 ,  G11C11/4093 ,  G11C11/4076 ,  G11C5/04

CPC classification number: G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

Abstract: A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.

公开(公告)号：US20170092379A1

公开(公告)日：2017-03-30

申请号：US15207557

申请日：2016-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Hyung Kim ,  Huichong Shin ,  Seokil Kim ,  Young Yun ,  Jonghyoung Lim ,  Youkeun Han

IPC: G11C29/34 ,  G06F12/1009 ,  G06F3/06 ,  G11C11/4093 ,  G11C11/4076

CPC classification number: G11C29/34 ,  G06F3/0613 ,  G06F3/0647 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0868 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/1024 ,  G11C5/04 ,  G11C7/1045 ,  G11C7/109 ,  G11C11/4076 ,  G11C11/4093 ,  G11C29/06 ,  G11C29/26 ,  G11C2029/0407

Abstract: A method of operating a memory module including a plurality of semiconductor memory devices organized into a multi-rank memory on a DIMM and a memory buffer included on the DIMM, operatively coupled to the multi-rank memory, can be provided by mapping an access to the DIMM from a memory controller to semiconductor memory devices included in more than one rank within the multi-rank memory based on a mode register set signal and selectively linking rank control signals during a parallel bit test operation to the more than one rank within the multi-rank memory plurality of semiconductor memory devices.