公开(公告)号：US09330791B2

公开(公告)日：2016-05-03

申请号：US14326966

申请日：2014-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangyeun Cho

IPC: G11C29/00 ,  G11C29/50 ,  G11C11/40

CPC classification number: G11C29/50016 ,  G06F12/126 ,  G06F2212/1028 ,  G06F2212/1032 ,  G06F2212/1044 ,  G11C7/1009 ,  G11C11/40 ,  G11C29/76

Abstract: A memory system includes a memory controller configured to replace a memory block including a failed memory cell with a unit cache block of a cache memory in response to detection of the failed memory cell in the memory block. The unit cache block is smaller than a minimum size of a memory cell array capable of being blocked by an operating system, and the unit cache block has substantially the same storage capacity as the memory block.

Abstract translation: 存储器系统包括存储器控制器，其被配置为响应于检测到存储器块中的故障存储器单元而将包括故障存储器单元的存储器块与高速缓冲存储器的单元高速缓存块替换。 单元高速缓存块小于能够被操作系统阻塞的存储单元阵列的最小尺寸，并且单元高速缓存块具有与存储块大致相同的存储容量。

公开(公告)号：US10810016B2

公开(公告)日：2020-10-20

申请号：US15156855

申请日：2016-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bon Cheol Gu ,  Duckho Bae ,  Jong Hyun Yoon ,  Jinyoung Lee ,  Insoon Jo ,  MoonSang Kwon ,  Sungho Yoon ,  Sangyeun Cho

IPC: G06F9/00 ,  G06F15/177 ,  G06F9/4401

Abstract: A method of operating a computing device includes a storage device receiving a request to execute an application instance, and executing the application instance at the storage device in response to the received request by the storage device. The application instance includes a plurality of storage instances connected with one another, and at least one of the plurality of storage instances is connected to a host device.

公开(公告)号：US10440112B2

公开(公告)日：2019-10-08

申请号：US15254400

申请日：2016-09-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joonho Baek ,  Hanjoon Kim ,  Jeonguk Kang ,  Dong-Uk Kim ,  Seungjun Yang ,  DuckJoo Lee ,  JinHo Yi ,  Yong-Taek Jeong ,  Sangyeun Cho

IPC: G06F15/16 ,  H04L29/08 ,  G06F12/02 ,  G06F9/50 ,  H04L29/06

Abstract: A server device includes a plurality of interface circuits configured to connect with a network, and perform format conversion between network packets and data chunks, the network packets being packets communicated with the network, the data chunks complying with an internal format; a plurality of memory modules operating independently of each other; and a switch circuit connected between the plurality of interface circuits and the plurality of memory modules, the switch circuit being configured to select at least one memory module from among the plurality of memory modules based on an attribute of a first data chunk transmitted from the plurality of interface circuits and, send the first data chunk to the selected memory module, wherein the selected at least one memory module is configured to, decode the first data chunk, and perform a read or write operation associated with the first data chunk based on the decoding result.

公开(公告)号：US09978440B2

公开(公告)日：2018-05-22

申请号：US15529587

申请日：2014-11-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangyeun Cho

IPC: G11C7/10 ,  G11C11/408 ,  G11C11/406

CPC classification number: G11C11/4082 ,  G11C11/406 ,  G11C11/408

Abstract: A method of managing a semiconductor memory is provided which includes sampling a row address from an access stream on a memory cell array according to a sampling period; determining whether the sampled row address is an address corresponding to a target row which is most frequently accessed, based on probability information; and executing a refresh operation on rows adjacent to the target row.