公开(公告)号：US20220399864A1

公开(公告)日：2022-12-15

申请号：US17746856

申请日：2022-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Omar Abdulmonem Mohamed Elsayed ,  Venumadhav Bhagavatula ,  Tienyu Chang ,  Siu-Chuang Ivan Lu ,  Sangwon Son

IPC: H03G3/30 ,  H03F3/45 ,  H03K5/01

Abstract: A variable gain amplifier includes a first transconductor circuit coupled to a first input terminal, a first output terminal, and a second output terminal of the variable gain amplifier, the first transconductor circuit including: a plurality of positive coefficient transistors coupled to the first output terminal and configured to selectively conduct current in response to a first binary code, a plurality of negative coefficient transistors coupled to the second output terminal and configured to selectively conduct current in response to a second binary code, and a plurality of amplifying transistors, each having a gate electrode coupled to the first input terminal, a first electrode coupled to a ground reference, and a second electrode coupled to a pair of coefficient transistors including one of the plurality of positive coefficient transistors and one of the plurality of negative coefficient transistors.

公开(公告)号：US12074575B2

公开(公告)日：2024-08-27

申请号：US17746856

申请日：2022-05-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Omar Abdulmonem Mohamed Elsayed ,  Venumadhav Bhagavatula ,  Tienyu Chang ,  Siu-Chuang Ivan Lu ,  Sangwon Son

IPC: H03G3/30 ,  H03F3/45 ,  H03K5/00 ,  H03K5/01

CPC classification number: H03G3/30 ,  H03F3/45475 ,  H03K5/01 ,  H03G2201/103 ,  H03K2005/00286

Abstract: A variable gain amplifier includes a first transconductor circuit coupled to a first input terminal, a first output terminal, and a second output terminal of the variable gain amplifier, the first transconductor circuit including: a plurality of positive coefficient transistors coupled to the first output terminal and configured to selectively conduct current in response to a first binary code, a plurality of negative coefficient transistors coupled to the second output terminal and configured to selectively conduct current in response to a second binary code, and a plurality of amplifying transistors, each having a gate electrode coupled to the first input terminal, a first electrode coupled to a ground reference, and a second electrode coupled to a pair of coefficient transistors including one of the plurality of positive coefficient transistors and one of the plurality of negative coefficient transistors.