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公开(公告)号:US20190148521A1
公开(公告)日:2019-05-16
申请号:US16170842
申请日:2018-10-25
Applicant: Samsung Electronics Co., Ltd.
Inventor: Gun Ho JO , Dae Joung KIM , Jae Mun KIM , Moon Han PARK , Tae Ho CHA , Jae Jong HAN
Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.
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公开(公告)号:US20200243398A1
公开(公告)日:2020-07-30
申请号:US16848228
申请日:2020-04-14
Applicant: Samsung Electronics Co., Ltd.
Inventor: Gun Ho JO , Dae Joung KIM , Jae Mun KIM , Moon Han PARK , Tae Ho CHA , Jae Jong HAN
IPC: H01L21/8238 , H01L21/02 , H01L29/66 , H01L29/78 , H01L29/423 , H01L21/84 , H01L21/8234 , H01L29/786
Abstract: A method for fabricating a semiconductor device includes forming a fin type pattern protruding from a substrate and extending in a first direction, forming a field insulating layer covering a limited portion of the fin type pattern on the substrate such that the field insulating layer exposes a separate limited portion of the fin type pattern, forming a gate structure on the field insulating layer and the fin type pattern, the gate structure extending in a second direction, the second direction different from the first direction, forming a first barrier layer containing a nitrogen element in a first region of the field insulating layer, wherein the first region is exposed by the gate structure, adjacent to the gate structure and extending in the second direction and forming a gate spacer on the first barrier layer and on a side wall of the gate structure.
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