公开(公告)号：US11120603B2

公开(公告)日：2021-09-14

申请号：US16538819

申请日：2019-08-12

申请人： Samsung Electronics Co., Ltd.

发明人： Tejash M. Shah ,  Mark Greenberg

IPC分类号： G06T15/50 ,  G06T15/00 ,  G06F11/34 ,  G06F9/48 ,  G06F9/355 ,  G06F9/38 ,  G06F9/30

摘要： A shader core includes a first processing element (PE), a second processing element, a register file and a warp sequencing unit. The first PE includes a first predetermined number of execution units, and the second PE includes a second predetermined number of execution units in which the second predetermined number of execution units is less than the first predetermined number of execution units. The register file shared by the first PE and the second PE. The warp sequencer unit (WSQ) is coupled to the first PE and to the second PE and schedules an instruction trace to execute on the first PE or the second PE based on information contained in a trace header of the instruction trace. The information contained in the trace header indicates whether the instruction trace is executable on the second PE.