公开(公告)号：US11831276B1

公开(公告)日：2023-11-28

申请号：US17959795

申请日：2022-10-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kishan Reddy Gonapati ,  Aswani Aditya Kumar Tadinada

IPC: H03B5/24

CPC classification number: H03B5/24

Abstract: According to at least some example embodiments of the inventive concepts, an RC oscillator includes an oscillator core including a timing-circuit that includes a plurality of matched current sources, a plurality of capacitors, and a resistor, a first continuous time comparator, and a Schmitt trigger; and an analog circuit connected to the oscillator core including a second continuous time comparator representing a replica of the first continuous time comparator, and an EX-OR gate, wherein the analog circuit is configured to pass a clock signal of the oscillator core through the second continuous time comparator and obtaining a delayed clock signal representing a comparator delay, extract the comparator delay of the first continuous time comparator based on feeding the clock signal and the obtained delayed clock signal to the EX-OR gate, and charge the plurality of capacitors connected to the first continuous time comparator.

公开(公告)号：US11381232B2

公开(公告)日：2022-07-05

申请号：US17196478

申请日：2021-03-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Vasu Bevara ,  Aswani Aditya Kumar Tadinada ,  Kishan Reddy Gonapati

IPC: H03K5/156 ,  H03K5/131 ,  H03K5/133

Abstract: The inventive concepts relate to methods for duty cycle correction of an input signal and circuits thereof. The method comprising following operations of generating, a plurality of intermediate delayed input signals, each delayed by at least a unit delay, through a delay line driven by the input signal, selecting from among the plurality of delayed input signals, through a first control signal, where the selection is based on number of unit delays in the input signal, generating at least an incremented duty signal and a decremented duty signal based on the selected delayed signals and the input signal, generating, a corrected duty cycle based on the selection of at least one of: the incremented duty cycle or decremented duty cycle by providing a second control signal. The inventive concepts offer low power consumption and low area for correction or adjustment of the duty cycle of the input signal with higher probability or guaranteed monotonicity.