SYSTEMS AND METHODS FOR PROVIDING ASYNCHRONOUS READ/WRITE SUPPORT IN DDR CONTROLLERS

    公开(公告)号:US20250028477A1

    公开(公告)日:2025-01-23

    申请号:US18655716

    申请日:2024-05-06

    Abstract: A system and method for implementing asynchronous READ/WRITE operations in a Double Data Rate (DDR) controller to reduce Dynamic Random Access Memory (DRAM) access latency. The system provides a program configurable interface to the DDR controller for pre-fetching data from a memory address of interest into cache, for serving an asynchronous READ operation. The asynchronous READ operation minimizes or reduces pre-charge latency, Row Address Select (RAS) latency, and Column Address Select (CAS) latency. The system provides a program configurable interface to the DDR controller the read operation or the write operation being for providing buffer data directly to the DDR controller to handle an asynchronous WRITE operation.

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