公开(公告)号：US20240081083A1

公开(公告)日：2024-03-07

申请号：US18302832

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junhoe Kim ,  Hyunchul Shin ,  Jayeong Hyeon

IPC: H10B61/00

CPC classification number: H10B61/00

Abstract: A semiconductor device includes a substrate including cell and peripheral regions, and a boundary region therebetween, a lower insulating layer on the cell region and extending onto the boundary and peripheral regions, data storage patterns on the lower insulating layer on the cell region, a cell insulating layer on the lower insulating layer on the cell region and on the data storage patterns, a first upper insulating layer on the cell insulating layer, peripheral conductive lines on the lower insulating layer on the peripheral region, and a peripheral insulating layer on the lower insulating layer on the peripheral region and on the peripheral conductive lines. The peripheral insulating layer extends onto the lower insulating layer on the boundary region to be in contact with side surfaces of the cell insulating layer and the first upper insulating layer. The peripheral insulating layer includes a material different from the cell insulating layer.