公开(公告)号：US20220408001A1

公开(公告)日：2022-12-22

申请号：US17669731

申请日：2022-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo HWANG ,  Homin KANG ,  Jaeuk AHN ,  Serhoon LEE

IPC: H04N5/232 ,  G06F9/48

Abstract: An image signal processor includes a command queue circuit, an image processing engine and an interrupt control circuit. The command queue circuit stores a plurality of commands and sequentially provides the plurality of commands one by one. Each command of the plurality of commands includes an interrupt control value corresponding to each image unit of a plurality of image units. The plurality of commands are received from a control processor. The image processing engine receives the plurality of image units and sequentially processes the plurality of image units based on the plurality of commands sequentially provided from the command queue circuit. The interrupt control circuit receives the interrupt control value from the command queue circuit, determines one or more output interrupt event signals among a plurality of interrupt event signals based on the interrupt control value and generates an interrupt signal based on the output interrupt event signals.

公开(公告)号：US20240313889A1

公开(公告)日：2024-09-19

申请号：US18594878

申请日：2024-03-04

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jinwoo HWANG

IPC: H04L1/00 ,  G06F11/10

CPC classification number: H04L1/0061 ,  G06F11/1004

Abstract: A cyclic redundancy check (CRC) system and a CRC method are provided. The CRC system includes a data folding processing circuit and a CRC processing circuit. The data folding processing circuit includes a first bit fold circuit configured to fold first input data into first fold data, a second bit fold circuit configured to fold second input data into second fold data, and a stream fold circuit configured to generate first fold streaming data based on the first fold data and the second fold data. The CRC processing circuit includes a first flip-flop configured to receive and store first dividend data of a first cycle, a second flip-flop configured to receive and store the first fold streaming data of the first cycle, and a CRC logic configured to perform a CRC operation on the first dividend data and the first fold streaming data.