公开(公告)号：US20140322916A1

公开(公告)日：2014-10-30

申请号：US14325080

申请日：2014-07-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： JungWoo SEO ,  JinSeo CHOI ,  KyoungRyul YOON

IPC: H01L21/308

CPC classification number: H01L21/308 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/76816

Abstract: A semiconductor device is fabricated by forming first holes arranged along a first direction on an etch-target layer, forming dielectric patterns in the first holes, conformally forming a barrier layer on the dielectric patterns, forming a sacrificial layer on the barrier layer to define a first void, partially removing the sacrificial layer to expose the first void, anisotropically etching the barrier layer to form second holes below the first void, and etching portions of the etch-target layer located below the first and second holes to form contact holes. The first void may be formed on a first gap region confined by at least three of the dielectric patterns disposed adjacent to each other, and the sacrificial layer may include a material having a low conformality.

Abstract translation: 通过在蚀刻目标层上形成沿着第一方向布置的第一孔来形成半导体器件，在第一孔中形成电介质图案，在电介质图案上保形地形成阻挡层，在阻挡层上形成牺牲层， 第一空隙，部分地去除牺牲层以暴露第一空隙，各向异性地蚀刻阻挡层以在第一空隙下形成第二孔，以及蚀刻位于第一孔和第二孔下方的蚀刻靶层的部分以形成接触孔。 可以在由彼此相邻布置的至少三个电介质图案限制的第一间隙区域上形成第一空隙，并且牺牲层可以包括具有低共形性的材料。