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公开(公告)号：US20190095782A1
公开(公告)日：2019-03-28
申请号：US15981440
申请日：2018-05-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Ook Song
Abstract: A device includes a first divider circuit connected to a first data lane and configured to receive a first data lane value having a first index, to receive a second index corresponding to a second data lane value from a second data lane, and to selectively output a first adding value or the first data lane value based on whether the first index is equal to the second index and a first adder circuit connected to the second data lane and the first divider circuit and configured to receive the first adding value from the first divider circuit, to receive the second data lane value, and to add the first adding value to the second data lane value to generate an addition result.
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公开(公告)号：US09257990B2
公开(公告)日：2016-02-09
申请号：US14543921
申请日：2014-11-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Ook Song
Abstract: A clock dividing device includes an accumulator that accumulates a first accumulated value and a denominator value and stores a second accumulated value, a register that stores a delayed accumulated value obtained by delaying the second accumulated value, a first comparison operation unit that performs a comparative operation on the second accumulated value and a numerator value and stores the second accumulated value as a greater value if the second accumulated value is greater than or equal to the numerator value, a second comparison operation unit that performs a comparative operation on the delayed accumulated value and the numerator value and stores the delayed accumulated value as a delay greater value if the delayed accumulated value is greater than or equal to the numerator value, and a third comparison operation unit that performs a comparative operation on the greater value and the delay greater value and determines the shape of a clock, wherein the shape of the clock is one of a bypass, a rising edge, and a falling edge.
Abstract translation: 时钟分配装置包括累加第一累加值和分母值并存储第二累加值的累加器，存储通过延迟第二累积值而获得的延迟累加值的寄存器;执行比较操作的第一比较运算单元 第二累计值和分子值，并且如果第二累加值大于或等于分子值，则将第二累积值存储为较大值;第二比较运算单元，对延迟累积值进行比较运算;以及 如果所述延迟累积值大于或等于所述分子值，则所述分子值并将所述延迟累加值存储为延迟更大值;以及第三比较运算单元，对所述更大值和所述延迟较大值进行比较运算，以及 确定时钟的形状，其中时钟的形状是一个 旁路，上升沿和下降沿。
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公开(公告)号：US20150236701A1
公开(公告)日：2015-08-20
申请号：US14543921
申请日：2014-11-18
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jin-Ook Song
IPC: H03K21/02
Abstract: A clock dividing device includes an accumulator that accumulates a first accumulated value and a denominator value and stores a second accumulated value, a register that stores a delayed accumulated value obtained by delaying the second accumulated value, a first comparison operation unit that performs a comparative operation on the second accumulated value and a numerator value and stores the second accumulated value as a greater value if the second accumulated value is greater than or equal to the numerator value, a second comparison operation unit that performs a comparative operation on the delayed accumulated value and the numerator value and stores the delayed accumulated value as a delay greater value if the delayed accumulated value is greater than or equal to the numerator value, and a third comparison operation unit that performs a comparative operation on the greater value and the delay greater value and determines the shape of a clock, wherein the shape of the clock is one of a bypass, a rising edge, and a falling edge.
Abstract translation: 时钟分配装置包括累加第一累加值和分母值并存储第二累加值的累加器，存储通过延迟第二累积值而获得的延迟累加值的寄存器;执行比较操作的第一比较运算单元 第二累计值和分子值，并且如果第二累加值大于或等于分子值，则将第二累积值存储为较大值;第二比较运算单元，对延迟累积值进行比较运算;以及 如果所述延迟累积值大于或等于所述分子值，则所述分子值并将所述延迟累加值存储为延迟更大值;以及第三比较运算单元，对所述更大值和所述延迟较大值进行比较运算，以及 确定时钟的形状，其中时钟的形状是一个 旁路，上升沿和下降沿。
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4.发明授权公开(公告)号：US10481668B2
公开(公告)日：2019-11-19
申请号：US15677050
申请日：2017-08-15
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jin-Ook Song , Yun-Ju Kwon , Dong-Sik Cho , Byung-Tak Lee
IPC: G06F1/32 , G06F1/3225 , G06F15/78 , G06F1/3296 , G06F1/3287 , G06F1/3234 , G11C5/14
Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.
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Patent Agency Ranking
公开(公告)号：US10372156B2
公开(公告)日：2019-08-06
申请号：US15388366
申请日：2016-12-22
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youn-Sik Choi , Jin-Ook Song , Ho-Yeon Jeon , Jae-Gon Lee
Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.
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6.发明授权公开(公告)号：US12271247B2
公开(公告)日：2025-04-08
申请号：US18500563
申请日：2023-11-02
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jin-Ook Song , Yun-Ju Kwon , Dong-Sik Cho , Byung-Tak Lee
IPC: G06F1/32 , G06F1/3225 , G06F1/3234 , G06F1/3287 , G06F1/3296 , G06F15/78 , G11C5/14
Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.
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7.发明授权公开(公告)号：US11836029B2
公开(公告)日：2023-12-05
申请号：US17827847
申请日：2022-05-30
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jin-Ook Song , Yun-Ju Kwon , Dong-Sik Cho , Byung-Tak Lee
IPC: G06F1/32 , G11C5/14 , G06F1/3225 , G06F15/78 , G06F1/3296 , G06F1/3287 , G06F1/3234
CPC classification number: G06F1/3225 , G06F1/3275 , G06F1/3287 , G06F1/3296 , G06F15/7821 , G11C5/14
Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.
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8.发明授权公开(公告)号：US11347292B2
公开(公告)日：2022-05-31
申请号：US16670026
申请日：2019-10-31
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jin-Ook Song , Yun-Ju Kwon , Dong-Sik Cho , Byung-Tak Lee
IPC: G06F1/32 , G06F1/3225 , G06F15/78 , G06F1/3296 , G06F1/3287 , G06F1/3234 , G11C5/14
Abstract: A system on chip (SoC) adjusts power of a memory through a handshake. The SoC includes a memory controller and a power manager. The memory controller is configured to control a memory. The power manager is configured to manage a supply power level of the memory. The memory controller is configured to output, to the power manager, a memory access level indicating a frequency of accesses to the memory. The power manager is configured to adjust the supply power level of the memory according to the memory access level.
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公开(公告)号：US10901452B2
公开(公告)日：2021-01-26
申请号：US16512849
申请日：2019-07-16
Applicant: Samsung Electronics Co., Ltd.
Inventor： Youn-Sik Choi , Jin-Ook Song , Ho-Yeon Jeon , Jae-Gon Lee
Abstract: A system-on-chip (SoC) comprises a clock management unit (CMU) including a first clock generator and a second clock generator, the first and second clock generators being configured to generate clock signals. The SoC comprises at least one logic block configured to request the clock signals from the CMU according to a full handshake method and receive the clock signals from the CMU in response to the request. The first clock generator and the second clock generator are configured to communicate according to the full handshake method.
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