公开(公告)号：US20220293206A1

公开(公告)日：2022-09-15

申请号：US17827845

申请日：2022-05-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG HYUK LEE

IPC: G11C29/42 ,  G11C11/16 ,  G06F11/10 ,  G11C29/44

Abstract: A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation.

公开(公告)号：US20210265003A1

公开(公告)日：2021-08-26

申请号：US17035917

申请日：2020-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JUNG HYUK LEE

IPC: G11C29/42 ,  G11C11/16 ,  G11C29/44 ,  G06F11/10

Abstract: A test method for a memory device including a plurality of memory cells includes generating a first test pattern, performing a first pattern write operation of writing the first test pattern in the plurality of memory cells, reading first data from the plurality of memory cells in which the first test pattern was written, generating a second test pattern based on the first data, and performing a second pattern write operation of writing the second test pattern in the plurality of memory cells. The second test pattern is generated such that a write operation is skipped with regard to failure cells from among the plurality of memory cells at which a write failure occurs, during the second pattern write operation.

公开(公告)号：US20200005847A1

公开(公告)日：2020-01-02

申请号：US16262366

申请日：2019-01-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsung Jung ,  HYEMIN SHIN ,  YOONJONG SONG ,  JUNG HYUK LEE

IPC: G11C11/16 ,  H01L27/22 ,  H01L43/02

Abstract: Disclosed is a memory device. The memory device includes a memory cell array that includes a target cell, a row decoder that drive a word line, and a write driver and sense amplifier that are configured to drive a bit line and a source line. The row decoder is configured to drive the word line in a first program operation and a second program operation. Between a start of the first program operation and an end of the second program operation, the write driver and sense amplifier are configured to continuously drive a bit line connected to the target cell with a second driving voltage or drive a source line connected to the target cell with a third driving voltage.