公开(公告)号：US20210294365A1

公开(公告)日：2021-09-23

申请号：US17069500

申请日：2020-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SUNGMIN YOO ,  Joowon Park ,  Tae-Hwang Kong ,  Sangho Kim ,  Hyunmyoung Kim ,  Jaeseung Lee

IPC: G05F1/46 ,  G05F1/565 ,  G06F1/3206 ,  G05F3/16

Abstract: A power manager circuit is provided. The power manager circuit includes a bandgap reference circuit, first and second monitoring circuits, and a reference buffer. The bandgap reference circuit generates a first voltage, based on an external voltage that is external to the power manager circuit. The first monitoring circuit determines a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range. The reference buffer generates a second voltage, based on the first voltage. The second monitoring circuit determines a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.

公开(公告)号：US11650232B2

公开(公告)日：2023-05-16

申请号：US17872363

申请日：2022-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheolhwan Lim ,  Junhee Shin ,  Haejung Choi ,  Kwangho Kim ,  Hyunmyoung Kim

IPC: G01R19/165 ,  H03K17/687 ,  H03K3/037 ,  G06F1/24 ,  G06F1/28

CPC classification number: G01R19/165 ,  G06F1/24 ,  G06F1/28 ,  H03K3/037 ,  H03K17/6872

Abstract: An electronic device includes circuitry configured to output a first output signal shifting to a logic high level at a first time in response to a supply voltage reaching a first voltage level, output a second output signal shifting to a logic high level at a second time occurring after the first time in response to the supply voltage reaches a second level higher than the first level; and the circuitry includes an AND gate circuit configured to output a reset signal based on the first output signal and the second output signal.

公开(公告)号：US11543841B2

公开(公告)日：2023-01-03

申请号：US17069500

申请日：2020-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungmin Yoo ,  Joowon Park ,  Tae-Hwang Kong ,  Sangho Kim ,  Hyunmyoung Kim ,  Jaeseung Lee

IPC: G05F1/46 ,  G05F3/16 ,  G06F1/3206 ,  G05F1/565

Abstract: A power manager circuit is provided. The power manager circuit includes a bandgap reference circuit, first and second monitoring circuits, and a reference buffer. The bandgap reference circuit generates a first voltage, based on an external voltage that is external to the power manager circuit. The first monitoring circuit determines a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range. The reference buffer generates a second voltage, based on the first voltage. The second monitoring circuit determines a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.