公开(公告)号：US20200295023A1

公开(公告)日：2020-09-17

申请号：US16886021

申请日：2020-05-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Young-Bae YOON ,  Joong-Shik SHIN ,  Kwang-Ho KIM ,  Hyun-Mog PARK

IPC: H01L27/11565 ,  H01L27/11582 ,  H01L27/11575 ,  H01L27/11568 ,  H01L27/11578

Abstract: A vertical memory device includes a channel, gate lines, and a cutting pattern, respectively, on a substrate. The channel extends in a first direction substantially perpendicular to an upper surface of the substrate. The gate lines are spaced apart from each other in the first direction. Each of the gate lines surrounds the channel and extends in a second direction substantially parallel to the upper surface of the substrate. The cutting pattern includes a first cutting portion extending in the first direction and cutting the gate lines, and a second cutting portion crossing the first cutting portion and merged with the first cutting portion.