公开(公告)号：US20230035899A1

公开(公告)日：2023-02-02

申请号：US17733051

申请日：2022-04-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun LEE ,  Suk Hoon KIM ,  Hyo-Sub KIM

IPC: H01L27/108

Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.

公开(公告)号：US20250071970A1

公开(公告)日：2025-02-27

申请号：US18942899

申请日：2024-11-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun LEE ,  Suk Hoon KIM ,  Hyo-Sub KIM

IPC: H10B12/00

Abstract: A semiconductor memory device with an improved electric characteristic and reliability is provided. The semiconductor memory device including a substrate including an active region defined by device separation film, the active region including a first part and second parts, the second parts being on two opposite sides of the first part, respectively a bit line extending on the substrate and across the active region, and a bit line contact between the substrate and the bit line and connected to the first part of the active region may be provided. The bit line contact includes a first ruthenium pattern, and a width of upper surface of the first ruthenium pattern is smaller than a width of bottom surface of the first ruthenium pattern.

公开(公告)号：US20240397707A1

公开(公告)日：2024-11-28

申请号：US18381785

申请日：2023-10-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangkyu SUN ,  Goro CHOI ,  Hyo-Sub KIM ,  Junhyeok AHN ,  Eunkyung CHA ,  Dongmin CHOI ,  Sanghyun CHOI

IPC: H10B12/00 ,  H01L29/423

Abstract: A semiconductor memory device includes a substrate having a cell array area and a core area near the cell array area, the cell array area including a direct contact hole exposing an active region, a buried contact in the cell array area, the buried contact being connected to a storage element, a direct contact in the cell array area, the direct contact including an upper layer and a lower layer, the upper layer including a metal, and the lower layer being in the direct contact hole in direct contact with the active region and including a silicide of the metal, bit lines in contact with the upper layer of the direct contact, and word lines crossing the bit lines.

公开(公告)号：US20230422486A1

公开(公告)日：2023-12-28

申请号：US18109442

申请日：2023-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Jongmin KIM ,  Hyo-Sub KIM ,  Hui-Jung KIM ,  Sohyun PARK ,  Junhyeok AHN ,  Chan-Sic YOON ,  Myeong-Dong LEE ,  Woojin JEONG ,  Wooyoung CHOI

IPC: H10B12/00

CPC classification number: H10B12/482 ,  H10B12/34 ,  H10B12/053 ,  H10B12/485

Abstract: A semiconductor device includes a cell active pattern including a first portion and a second portion that are spaced apart from each other; a gate structure between the first portion and the second portion of the cell active pattern; a bit-line contact on the first portion of the cell active pattern; a connection pattern on the second portion of the cell active pattern; and a cell separation pattern in contact with the bit-line contact and the connection pattern, wherein the cell separation pattern includes a first sidewall in contact with the connection pattern and a second sidewall in contact with the bit-line contact, an upper portion of the second sidewall of the cell separation pattern is in contact with the bit-line contact, and a lower portion of the second sidewall of the cell separation pattern is spaced apart from the bit-line contact.

公开(公告)号：US20230112907A1

公开(公告)日：2023-04-13

申请号：US17861479

申请日：2022-07-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyo-Sub KIM ,  Junhyeok AHN ,  Myeong-Dong LEE ,  Hui-Jung KIM ,  Kiseok LEE ,  Jihun LEE ,  Yoosang HWANG

IPC: H01L27/108

Abstract: A semiconductor memory device and a method of fabricating a semiconductor memory device, the device including a first impurity region in a substrate; a first bit line that crosses over the substrate and is connected to the first impurity region; a bit-line contact between the first bit line and the first impurity region; and a contact ohmic layer between the bit-line contact and the first impurity region, wherein a width of a bottom surface of the bit-line contact is greater than a width of a bottom surface of the contact ohmic layer.