公开(公告)号：US20250081585A1

公开(公告)日：2025-03-06

申请号：US18952625

申请日：2024-11-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaejin LEE ,  Youngjun KIM ,  Hunyoung BARK ,  Taekyung YOON ,  Eunok LEE

IPC: H01L29/49 ,  H10B12/00

Abstract: A gate structure includes a first gate electrode including a metal, a gate barrier pattern on the first gate electrode and including a metal nitride, and a second gate electrode on the gate barrier pattern. The gate structure is buried in an upper portion of a substrate. The gate barrier pattern has a flat upper surface and an uneven lower surface.

公开(公告)号：US20230290681A1

公开(公告)日：2023-09-14

申请号：US17957473

申请日：2022-09-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taekyung YOON ,  Youngjun KIM ,  Hunyoung BARK ,  Eun-Ok LEE ,  Jaejin LEE ,  Dongju CHANG

IPC: H01L21/768 ,  H01L21/67 ,  H01L21/3213

CPC classification number: H01L21/76877 ,  H01L21/76829 ,  H01L21/67103 ,  H01L21/3213 ,  H01L21/76856

Abstract: Provided is a method of fabricating a semiconductor device including forming a device isolation layer defining active regions on a substrate and forming gate lines intersecting the active regions and buried in the substrate. The forming of the gate lines includes forming a trench crossing the active regions in the substrate, forming a conductive layer filling the trench, and performing a heat treatment process on the conductive layer. The conductive layer includes a nitride of a first metal. Nitrogen atoms in the conductive layer are diffused toward an outer surface and a lower surface of the conductive layer by the heat treatment process.