公开(公告)号：US20170344447A1

公开(公告)日：2017-11-30

申请号：US15681559

申请日：2017-08-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-hoon JEONG ,  Ho-young KIM ,  Soo-jung RYU

IPC: G06F11/22 ,  G06F11/263 ,  G06F11/36

CPC classification number: G06F11/2236 ,  G06F11/263 ,  G06F11/3688

Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

公开(公告)号：US20180282581A1

公开(公告)日：2018-10-04

申请号：US15897261

申请日：2018-02-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Doo-sik MOON ,  Sang-hyun PARK ,  Bo-un YOON ,  Ho-young KIM ,  Se-jung PARK ,  Jae-hak LEE ,  Jin-myung HWANG

IPC: C09G1/02 ,  C09K3/14

CPC classification number: C09G1/02 ,  C09K3/1409 ,  C09K3/1463

Abstract: A slurry composition for chemical mechanical polishing, the slurry composition including ceramic polishing particles; a dispersion agent; a pH control agent and an additive having affinity with silicon nitride.

公开(公告)号：US20180101632A1

公开(公告)日：2018-04-12

申请号：US15718305

申请日：2017-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ho-young KIM

IPC: G06F17/50

CPC classification number: G06F17/5045

Abstract: Provided are a method of generating a functional coverage model from a hardware description language (HDL) code for a circuit design and performing verification of the circuit design by using the functional coverage model, and a computing system in which the method is performed.

公开(公告)号：US20150100833A1

公开(公告)日：2015-04-09

申请号：US14259481

申请日：2014-04-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seong-hoon JEONG ,  Ho-young KIM ,  Soo-jung RYU

IPC: G06F11/22 ,  G06F9/30

CPC classification number: G06F11/2236 ,  G06F11/263 ,  G06F11/3688

Abstract: A method and apparatus for generating a test bench for verifying a processor decoder are provided. The method including receiving an architecture description comprising processor decoder information, parsing the received architecture description into information for verifying the processor decoder, and generating the test bench to verify the processor decoder based on the parsed information.

Abstract translation: 提供了一种用于生成用于验证处理器解码器的测试台的方法和装置。 该方法包括接收包括处理器解码器信息的架构描述，将接收到的体系结构描述解析为用于验证处理器解码器的信息，以及生成测试台以根据解析的信息来验证处理器解码器。