Abstract:
A method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors includes controlling the deep power down mode in the multi-port semiconductor memory such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.
Abstract:
An apparatus and a method for identify an application to which a packet flow belongs in a communication system. In the method, characteristic information of a first application is selected. Bit lines of a position designated by a mask included in the characteristic information are examined from packets transferred via the packet flow. A ratio of the number of examination results of coincidence to the number of all input packets is calculated. When the ratio exceeds a first threshold included in the characteristic information, it is determined that the packet flow belongs to the first application.
Abstract:
Provided is a method for detecting an application in a wireless communication system. The method includes receiving and inspecting a packet; detecting flows from the packet using a predefined signature; granting a score to each of the detected flows, and summing the granted scores by integrating the detected flows for each application; comparing the summed score of the flows integrated for each application with a preset value; and determining that an application is detected, if the summed score is greater than the preset value.
Abstract:
A memory device includes a memory cell array, a column decoder, and a row decoder. The row decoder includes a first word line driver and a second word line driver. The first word line driver is configured to electrically coupled to a first set of antifuse memory cells coupled to a first word line. The second word line driver is configured to electrically coupled to a second set of antifuse memory cells coupled to a second word line. The first set of antifuse memory cells are arranged in first and third rows of the memory cell array, and the second set of antifuse memory cells are arranged in second and fourth rows of the memory cell array. The second row is arranged between the first and third rows.