公开(公告)号：US09311270B2

公开(公告)日：2016-04-12

申请号：US14197591

申请日：2014-03-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Won-Sub Kim ,  Yoonseo Choi ,  Hae-Woo Park

IPC: G06F9/46 ,  G06F15/78 ,  G06F9/48

CPC classification number: G06F15/7885 ,  G06F9/4881

Abstract: A scheduler and scheduling method perform scheduling for a reconfigurable architecture. The scheduling, performed by the scheduler, includes path information extracting including extracting direct path information and indirect path information between functional units in a reconfigurable array complying with predefined architecture requirements, based on architecture information of the reconfigurable array, command selecting including selecting a command from a data flow graph (DFG) showing commands to be executed by the reconfigurable array, and scheduling including scheduling the selected command based on the extracted direct path information and indirect path information.

Abstract translation: 调度器和调度方法对可重构架构执行调度。 由调度器执行的调度包括路径信息提取，包括基于可重配置阵列的体系结构信息，在可重配置阵列的可重构阵列中的功能单元之间提取直接路径信息和间接路径信息，命令选择包括从 显示由可重配置阵列执行的命令的数据流图（DFG），以及包括基于所提取的直接路径信息和间接路径信息来调度所选择的命令的调度。

公开(公告)号：US09632978B2

公开(公告)日：2017-04-25

申请号：US13827280

申请日：2013-03-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hae-Woo Park ,  Won-Sub Kim

IPC: G06F9/30 ,  G06F15/80 ,  G06F9/45 ,  G06F15/78 ,  G06F9/38

CPC classification number: G06F15/80 ,  G06F8/4452 ,  G06F9/3012 ,  G06F9/3891 ,  G06F15/7867 ,  G06F15/8023

Abstract: A reconfigurable processor based on mini-cores (MCs) includes a plurality of MCs, each MC of the MCs including a group of function units (FUs), the group of FUs having a capability of executing a loop iteration independently. The MCs include a first MC configured to execute a first loop iteration, and a second MC configured to execute a second loop iteration.

公开(公告)号：US09753769B2

公开(公告)日：2017-09-05

申请号：US14160756

申请日：2014-01-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Woo Park ,  Suk-Jin Kim

IPC: G06F9/46 ,  G06F9/48 ,  G06F15/78 ,  G06F9/38

CPC classification number: G06F9/4881 ,  G06F9/3877 ,  G06F15/7867

Abstract: An apparatus and method for sharing a function logic between functional units and a reconfigurable processor are provided. The apparatus for sharing a function logic may include a storage which is configured to store data which is received from two or more functional units in order to share one or more function logics, and an arbitrator which is configured, based on a scheduling rule, to transmit the data stored in the storage into the function logic.

公开(公告)号：US20130246735A1

公开(公告)日：2013-09-19

申请号：US13827280

申请日：2013-03-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hae-Woo Park ,  Won-Sub Kim

IPC: G06F15/80

CPC classification number: G06F15/80 ,  G06F8/4452 ,  G06F9/3012 ,  G06F9/3891 ,  G06F15/7867 ,  G06F15/8023

Abstract: A reconfigurable processor based on mini-cores (MCs) includes a plurality of MCs, each MC of the MCs including a group of function units (FUs), the group of FUs having a capability of executing a loop iteration independently. The MCs include a first MC configured to execute a first loop iteration, and a second MC configured to execute a second loop iteration.

Abstract translation: 基于微型核心（MC）的可重构处理器包括多个MC，MC的每个MC包括一组功能单元（FU），该组具有独立地执行循环迭代的能力。 MC包括被配置为执行第一循环迭代的第一MC，以及被配置为执行第二循环迭代的第二MC。