公开(公告)号：US20250081430A1

公开(公告)日：2025-03-06

申请号：US18740045

申请日：2024-06-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae Young EOM ,  Chan-Sic YOON ,  Hyung Min KO ,  Ha Lim NOH ,  Hee Cheol SHIN

IPC: H10B12/00

Abstract: A semiconductor memory device includes: a substrate including a cell area, a peripheral area, and a boundary area; a storage pad connected to an active area in the cell area; a capacitor including a lower electrode, a first electrode support layer supporting the lower electrode, a capacitor dielectric, and an upper electrode; a peripheral gate on the peripheral area of the substrate; first peripheral contact plugs on both sides of the peripheral gate and connected to the substrate; a first interlayer insulating layer on the storage pad and the first peripheral contact plugs; a second interlayer insulating layer on the first interlayer insulating layer; and a first insulating layer on the second interlayer insulating layer, wherein the first insulating layer extends on the boundary area of the substrate, and a height of the first insulating layer is equal to or less than a height of the first electrode support layer.