公开(公告)号：US20240347080A1

公开(公告)日：2024-10-17

申请号：US18406726

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsuk Kang ,  Jeongsu Lee ,  Eunji An ,  Jungjune Park ,  Chiweon Yoon

IPC: G11C5/14

CPC classification number: G11C5/147

Abstract: A semiconductor device includes a first pull-up circuit connected between a first power node supplying a first power voltage and an output node through which a signal is output, and including a plurality of NMOS transistors; a second pull-up circuit connected in parallel to the first pull-up circuit between the first power node and the output node and including a plurality of PMOS transistors; and a control circuit outputting a first pull-up code to the first pull-up circuit and outputting the second pull-up code to the second pull-up circuit. In a first operating mode, the signal swings between a first low level lower than the first power voltage, and a first high level lower than ½ times the first power voltage, resistance of the first pull-up circuit is determined based on the first pull-up code, and resistance of the second pull-up circuit is determined based on the second pull-up code.