公开(公告)号：US20210165733A1

公开(公告)日：2021-06-03

申请号：US16913707

申请日：2020-06-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaeshin LEE ,  Eunhye OH ,  Jaechul PARK

IPC: G06F12/02 ,  G06F12/0891 ,  G06F13/16 ,  G06F9/30 ,  G06F9/54 ,  G06F11/14

Abstract: A device for writing data to a memory, the device including: a first write buffer having a first data width that matches a width of write data included in a write request and wherein the first write buffer is configured to store the write data as first data; a second write buffer having a second data width that matches a data width of the memory and is greater than the first data width; and a controller configured to, based on a write address included in the write request and an address of the second data stored in the second write buffer, write the first data stored in the first write buffer to the second write buffer and write the second data stored in the second write buffer to the memory.

公开(公告)号：US20250068517A1

公开(公告)日：2025-02-27

申请号：US18944088

申请日：2024-11-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye OH ,  Taewook PARK ,  Jisu KANG ,  Yongki LEE

IPC: G06F11/10 ,  G06F11/07

Abstract: Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.

公开(公告)号：US20230214297A1

公开(公告)日：2023-07-06

申请号：US18148061

申请日：2022-12-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunhye OH ,  Taewook PARK ,  Jisu KANG ,  Yongki LEE

IPC: G06F11/10 ,  G06F11/07

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/1004

Abstract: Provided is a storage device including a memory device configured to store original data; and a controller configured to control the memory device, the controller including a first error correction circuit configured to correct an error of the original data, and a second error correction circuit configured to correct an error of the original data, a maximum number of correctable error bits of the second error correction circuit being greater than a maximum number of correctable error bits of the first error correction circuit, a mapping memory configured to store at least some of parity bits generated by the second error correction circuit and store an address of the memory device at which the original data is stored; and a control block configured to control the first error correction circuit, the second error correction circuit, and the mapping memory.