公开(公告)号：US20200219934A1

公开(公告)日：2020-07-09

申请号：US16561675

申请日：2019-09-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： BYEONGJU BAE ,  Duckhee Lee

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00

Abstract: Disclosed are variable resistance memory devices and methods of fabricating the same. The variable resistance memory device may include: a plurality of memory cells, each comprising a variable resistance pattern and a switching pattern; a plurality of conductive lines to which the memory cell is connected; a bottom electrode connecting at least one of the conductive lines to the variable resistance pattern; and a spacer pattern formed on the bottom electrode to be in contact with the variable resistance pattern. The spacer pattern includes a dielectric material doped with an impurity.

公开(公告)号：US11177320B2

公开(公告)日：2021-11-16

申请号：US16561675

申请日：2019-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeongju Bae ,  Duckhee Lee

IPC: H01L27/24 ,  H01L23/528 ,  H01L45/00

Abstract: Disclosed are variable resistance memory devices and methods of fabricating the same. The variable resistance memory device may include: a plurality of memory cells, each comprising a variable resistance pattern and a switching pattern; a plurality of conductive lines to which the memory cell is connected; a bottom electrode connecting at least one of the conductive lines to the variable resistance pattern; and a spacer pattern formed on the bottom electrode to be in contact with the variable resistance pattern. The spacer pattern includes a dielectric material doped with an impurity.

公开(公告)号：US11882687B2

公开(公告)日：2024-01-23

申请号：US17368053

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsun Ryu ,  Duckhee Lee ,  Junwon Lee ,  Younseok Choi

IPC: H10B12/00

CPC classification number: H10B12/315

Abstract: A semiconductor device includes an active pattern on a substrate, a gate structure buried at an upper portion of the active pattern, a bit line structure on the active pattern, a spacer structure on a sidewall of the bit line structure, a contact plug structure contacting the spacer structure, an insulating interlayer structure partially penetrating through upper portions of the contact plug structure, the spacer structure and the bit line structure, and a capacitor on the contact plug structure. The spacer structure includes an air spacer including air. The insulating interlayer structure includes first and second insulating interlayers. The second insulating interlayer may include an insulation material different from that of the first insulating interlayer. A lower surface of the second insulating interlayer covers a top of the air spacer, and a lowermost surface of the first insulating interlayer is covered by the second insulating interlayer.