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    Device and method for sharing resource via bus
    1.
    发明授权
    Device and method for sharing resource via bus 有权

    公开(公告)号：US11914536B2

    公开(公告)日：2024-02-27

    申请号：US17579882

    申请日：2022-01-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongsik Cho

    IPC: G06F13/362 ,  G06F1/14

    CPC classification number: G06F13/362 ,  G06F1/14

    Abstract: The device described herein, which provides an interface between a plurality of master devices and a slave device, includes: a first timer configured to begin timing when a first access request is received from a first master device via a bus, and to be reset when a semaphore is allocated to the first master device; a second timer configured to begin timing when a second access request is received from a second master device via the bus, and to be reset when a semaphore is allocated to the second master device; and a controller configured to provide a first message to the first master device via the bus when a first expiration interval is measured by the first timer.

    Memory system and SoC including linear address remapping logic
    2.
    发明授权
    Memory system and SoC including linear address remapping logic 有权

    公开(公告)号：US11573716B2

    公开(公告)日：2023-02-07

    申请号：US16940687

    申请日：2020-07-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongsik Cho

    IPC: G06F3/06 ,  G06F12/02 ,  G06F12/06 ,  G06F15/78 ,  G06F13/42

    Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller dorms a linear access operation on the first or second memory device in response to receiving the remapped address.

    Integrity check device for safety sensitive data and electronic device including the same
    4.
    发明授权
    Integrity check device for safety sensitive data and electronic device including the same 有权

    公开(公告)号：US11599411B2

    公开(公告)日：2023-03-07

    申请号：US16943185

    申请日：2020-07-30

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongsik Cho

    IPC: G06F11/10 ,  G06F11/22

    Abstract: An integrity check device includes a register array processing circuitry which generates a current cyclic redundancy check (CRC) parity value by sequentially performing a CRC calculation on a plurality of safety sensitive data, stores a reference CRC parity value, outputs a check result signal indicating whether an error occurs by activating a first path and by comparing the current CRC parity value with the reference CRC parity value when the plurality of safety sensitive data are maintained and when an operation of updating the reference CRC parity value is unnecessary, and updates the reference CRC parity value to the current CRC parity value by activating a second path when at least one of the plurality of safety sensitive data is intentionally changed and when the operation of updating the reference CRC parity value is necessary.

    Memory system and SoC including linear address remapping logic
    5.
    发明授权
    Memory system and SoC including linear address remapping logic 有权

    公开(公告)号：US11169722B2

    公开(公告)日：2021-11-09

    申请号：US16215827

    申请日：2018-12-11

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongsik Cho

    IPC: G06F12/02 ,  G06F3/06 ,  G06F12/06 ,  G06F15/78 ,  G06F13/42

    Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

    Memory system and SoC including linear address remapping logic
    8.
    发明授权
    Memory system and SoC including linear address remapping logic 有权

    公开(公告)号：US10817199B2

    公开(公告)日：2020-10-27

    申请号：US15424019

    申请日：2017-02-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongsik Cho

    IPC: G06F3/06 ,  G06F15/78 ,  G06F12/06 ,  G06F12/02 ,  G06F13/42

    Abstract: A system-on-chip is connected to a first memory device and a second memory device. The system-on-chip comprises a memory controller configured to control an interleaving access operation on the first and second memory devices. A modem processor is configured to provide an address for accessing the first or second memory devices. A linear address remapping logic is configured to remap an address received from the modem processor and to provide the remapped address to the memory controller. The memory controller performs a linear access operation on the first or second memory device in response to receiving the remapped address.

    Integrity check device for safety sensitive data and electronic device including the same
    9.
    发明授权
    Integrity check device for safety sensitive data and electronic device including the same 有权

    公开(公告)号：US12229001B2

    公开(公告)日：2025-02-18

    申请号：US18179146

    申请日：2023-03-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongsik Cho

    IPC: G06F11/10 ,  G06F3/06 ,  G06F11/07 ,  G06F11/277 ,  G11C29/42 ,  G11C29/52 ,  H03M13/09

    Abstract: An integrity check device includes a register array processing circuitry which generates a current cyclic redundancy check (CRC) parity value by sequentially performing a CRC calculation on a plurality of safety sensitive data, stores a reference CRC parity value, outputs a check result signal indicating whether an error occurs by activating a first path and by comparing the current CRC parity value with the reference CRC parity value when the plurality of safety sensitive data are maintained and when an operation of updating the reference CRC parity value is unnecessary, and updates the reference CRC parity value to the current CRC parity value by activating a second path when at least one of the plurality of safety sensitive data is intentionally changed and when the operation of updating the reference CRC parity value is necessary.

    SHARED SLAVE ACCESS CONTROLLER, ELECTRONIC DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF
    10.
    发明申请
    SHARED SLAVE ACCESS CONTROLLER, ELECTRONIC DEVICE HAVING THE SAME, AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20240403246A1

    公开(公告)日：2024-12-05

    申请号：US18389008

    申请日：2023-11-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dongsik Cho

    IPC: G06F13/20

    Abstract: An electronic device is provided. The electronic device includes: a plurality of master devices; and a shared subsystem including: a system bus connected to the plurality of master devices; a shared slave device; and a shared slave access controller connected to the system bus, and configured to determine a master identification number corresponding to an access request received from a first master device of the plurality of master devices, determine whether or not to permit the first master device to access the shared slave device during an access window of the shared slave device based on the master identification number, and control access authority of the first master device during the access window.

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