公开(公告)号：US20230352429A1

公开(公告)日：2023-11-02

申请号：US18082886

申请日：2022-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoo CHOI ,  GUNHO CHANG

IPC: H01L23/00 ,  H01L23/58

CPC classification number: H01L24/05 ,  H01L23/585 ,  H01L24/03 ,  H01L24/80 ,  H01L2224/0508 ,  H01L2224/05541 ,  H01L2224/0557 ,  H01L2224/80097 ,  H01L2924/1431 ,  H01L2924/1434

Abstract: Disclosed is a semiconductor device comprising an upper pad surrounded by an upper dielectric layer, a lower pad in contact with the upper pad and the upper dielectric layer surrounded by a lower dielectric layer. The upper pad, the upper dielectric layer, the lower pad, and the lower dielectric layer define an upper space surrounding a lower portion of the upper pad and a lower space surrounding an upper portion of the lower pad. The upper space includes a first pad overlap section overlapping the lower pad and a first dielectric layer overlap section overlapping the lower dielectric layer. The lower pad includes a first protrusion part protruding toward the first pad overlap section of the upper space. The first protrusion part of the lower pad is at a level higher than that of a bottom surface of the upper dielectric layer.

公开(公告)号：US20220352138A1

公开(公告)日：2022-11-03

申请号：US17569302

申请日：2022-01-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoo CHOI

IPC: H01L25/18 ,  H01L23/498 ,  H01L23/48 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00

Abstract: A semiconductor package includes an interposer substrate; an upper semiconductor chip on a top surface of the interposer substrate, such that a bottom surface of the upper semiconductor chip faces the top surface of the interposer substrate, a chip stack on a bottom surface of the interposer substrate and including a plurality of stacked lower semiconductor chips, wherein each of the lower semiconductor chips includes a plurality of through vias therein, wherein a top surface of the chip stack faces the bottom surface of the interposer substrate, a molding layer that covers a sidewall of the chip stack, a sidewall of the interposer substrate, and a sidewall of the upper semiconductor chip, and a plurality of connection terminals disposed below a bottom surface of the chip stack opposite the top surface of the chip stack, and coupled to the through vias. The upper semiconductor chip is electrically connected through the interposer substrate to the through vias.

公开(公告)号：US20250149526A1

公开(公告)日：2025-05-08

申请号：US18825162

申请日：2024-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD

Inventor： Wonjung JANG ,  Dongjoo CHOI

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H10B80/00

Abstract: A semiconductor package includes: a buffer die; memory dies on the buffer die; a bonding layer between the memory dies; and a molding member disposed on the buffer die and the memory dies, wherein each of the memory dies includes: a first substrate having first and second surfaces; a first conductive pad and a first conductive connection member stacked on the first substrate; and a second conductive pad disposed on the first substrate, wherein the second conductive pad of a first memory die of the memory dies contacts the first conductive connection member of a second memory die of the memory dies. The first memory die is disposed under the second memory die. The first conductive pad includes a first conductive pattern and a second conductive pattern. The second conductive pad includes a third conductive pattern and a fourth conductive pattern. The fourth conductive pattern contacts the third conductive pattern.

公开(公告)号：US20160110056A1

公开(公告)日：2016-04-21

申请号：US14883940

申请日：2015-10-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohy HONG ,  Kyungwhoon CHEUN ,  Jisung OH ,  Kiseok LEE ,  Dongjoo CHOI

IPC: G06F3/0481 ,  G06F3/0484 ,  G06F3/0488

CPC classification number: G06F3/04812 ,  G06F3/04842 ,  G06F3/04883

Abstract: The present disclosure relates to a sensor network, Machine Type Communication (MTC), Machine-to-Machine (M2M) communication, and technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the above technologies, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. A method of providing a user interface (UI) by an electronic device is provided. The method includes displaying a control UI, receiving a first drag input via the displayed control UI, and, when a direction of the first drag input corresponds to a first direction, displaying a cursor UI at a preset location. According to an embodiment of the present disclosure, a UI through which an electronic device can easily receive a user input may be provided.

Abstract translation: 本公开涉及传感器网络，机器类型通信（MTC），机器对机器（M2M）通信和物联网技术（IoT）。 本发明可以应用于智能家居，智能建筑，智能城市，智能汽车，连接车，医疗保健，数字教育，智能零售，安全和安全服务等上述技术的智能化服务。 提供了一种通过电子设备提供用户界面（UI）的方法。 该方法包括显示控制UI，经由显示的控制UI接收第一拖动输入，并且当第一拖动输入的方向对应于第一方向时，在预设位置显示光标UI。 根据本公开的实施例，可以提供电子设备可以容易地接收用户输入的UI。

公开(公告)号：US20220246582A1

公开(公告)日：2022-08-04

申请号：US17495612

申请日：2021-10-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： GEOL NAM ,  GUNHO CHANG ,  CHUL-YONG JANG ,  Dongjoo CHOI

IPC: H01L25/065 ,  H01L25/18

Abstract: Disclosed is a semiconductor package comprising a lower semiconductor chip and upper semiconductor chips vertically stacked on a top surface of the lower semiconductor chip. The upper semiconductor chips include first upper semiconductor chips and a second upper semiconductor chip. The first upper semiconductor chips are between the lower semiconductor chip and the second upper semiconductor chip. A thickness of each of the first upper semiconductor chips is 0.4 to 0.95 times that of the lower semiconductor chip. A thickness of the second upper semiconductor chip is the same as or greater than that of the first upper semiconductor chip. A total number of the first and second upper semiconductor chips is 4n, wherein n is a natural number equal to or greater than three.

公开(公告)号：US20210343616A1

公开(公告)日：2021-11-04

申请号：US16953745

申请日：2020-11-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoo CHOI ,  Seungduk BAEK ,  Youngdeuk KIM

IPC: H01L23/367 ,  H01L25/065 ,  H01L23/522

Abstract: Provided is a semiconductor package including a lower semiconductor chip including a lower semiconductor substrate, a rear surface protecting layer covering a non-active surface of the lower semiconductor substrate, a plurality of lower via electrodes, and a plurality of rear surface signal pads and a plurality of rear surface thermal pads arranged on the rear surface protecting layer; an upper semiconductor chip including an upper semiconductor substrate, a wiring structure on an active surface of the upper semiconductor substrate, a front surface protecting layer that covers the wiring structure and has a plurality of front surface openings, and a plurality of signal vias and a plurality of thermal vias that fill the front surface openings; and a plurality of signal bumps connecting between the rear surface signal pads and the signal vias and a plurality of thermal bumps connecting between the rear surface thermal pads and the thermal vias.

公开(公告)号：US20240421143A1

公开(公告)日：2024-12-19

申请号：US18814589

申请日：2024-08-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoo CHOI

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes an interposer substrate; an upper semiconductor chip on a top surface of the interposer substrate, such that a bottom surface of the upper semiconductor chip faces the top surface of the interposer substrate, a chip stack on a bottom surface of the interposer substrate and including a plurality of stacked lower semiconductor chips, wherein each of the lower semiconductor chips includes a plurality of through vias therein, wherein a top surface of the chip stack faces the bottom surface of the interposer substrate, a molding layer that covers a sidewall of the chip stack, a sidewall of the interposer substrate, and a sidewall of the upper semiconductor chip, and a plurality of connection terminals disposed below a bottom surface of the chip stack opposite the top surface of the chip stack, and coupled to the through vias. The upper semiconductor chip is electrically connected through the interposer substrate to the through vias.

公开(公告)号：US20220115292A1

公开(公告)日：2022-04-14

申请号：US17341463

申请日：2021-06-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjoo CHOI

IPC: H01L23/38 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00

Abstract: Semiconductor chips may include a substrate; a protective layer on a first surface of the substrate, through electrodes extending through the substrate and the protective layer, and a Peltier structure including first through structures including first conductivity type impurities, and second through structures including second conductivity type impurities, which may extend through the substrate and the protective layer; pads on the protective layer and connected to the through electrodes, respectively, first connection wires connecting respective first ends of the first through structures to respective first ends of the second through structures, and second connection wires connecting respective second ends of the first through structures to respective second ends of one of the second through structures. The first through structures and the second through structures may be alternately connected to each other in series by the first connection wires and the second connection wires.

公开(公告)号：US20210143126A1

公开(公告)日：2021-05-13

申请号：US16899013

申请日：2020-06-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoo CHOI ,  Seungduk BAEK

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package may include a substrate, a chip stack disposed on the substrate, the chip stack including a plurality of first semiconductor chips vertically stacked on the substrate, a second semiconductor chip disposed on the substrate and horizontally spaced apart from the chip stack, and a third semiconductor chip disposed on the second semiconductor chip. An upper portion of the second semiconductor chip and a lower portion of the third semiconductor chip may contain an insulating element. The upper portion of the second semiconductor chip and the lower portion of the third semiconductor chip may contact each other at an interface between the second semiconductor chip and the third semiconductor chip and may constitute a single object formed of a same material.