公开(公告)号：US20140191785A1

公开(公告)日：2014-07-10

申请号：US14147184

申请日：2014-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Tae-Pyeong KIM ,  Han-Kyul LIM ,  Dong-Uk PARK

IPC: H03L7/00

CPC classification number: H03L1/027 ,  G04G3/022 ,  H03K3/011

Abstract: A frequency compensation apparatus includes a first counter setting a reference period using a main clock, a second counter sensing a change in the frequency of a sub clock using the reference period, and a frequency compensator providing a compensated frequency using information on the changed frequency of the sub clock. Related methods are also described.

Abstract translation: 频率补偿装置包括使用主时钟设定基准周期的第一计数器，使用基准周期检测子时钟的频率变化的第二计数器和使用关于改变频率的信息的频率补偿器 子时钟。 还描述了相关方法。

公开(公告)号：US20180091122A1

公开(公告)日：2018-03-29

申请号：US15584448

申请日：2017-05-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hye-Won SHIM ,  Dong-Uk PARK ,  Phil-Jae JEON ,  Sang-Woo PAE ,  Da AHN

IPC: H03K3/66 ,  H03K19/00 ,  H03K5/19

CPC classification number: H03K3/66 ,  G06F1/04 ,  H03K5/135 ,  H03K5/19 ,  H03K19/0002

Abstract: A clock switch device includes a control circuit and a tri-state buffer. The control circuit deactivates an output enable signal when a frequency of a clock signal varies and activates the output enable signal when the frequency of the clock signal is maintained without change. The tri-state buffer maintains an output electrode at a high impedance state when the output enable signal is deactivated and buffers the clock signal and outputs the buffered clock signal through the output electrode as an output clock signal when the output enable signal is activated.