公开(公告)号：US20220384291A1

公开(公告)日：2022-12-01

申请号：US17883726

申请日：2022-08-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： DONGHO KIM ,  Jongbo SHIM ,  Hwanpil PARK ,  Jangwoo LEE

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065

Abstract: A semiconductor package is disclosed. The disclosed semiconductor package includes a substrate having bonding pads at an upper surface thereof, a lower semiconductor chip, at least one upper semiconductor chip disposed on the lower semiconductor chip, and a dam structure having a closed loop shape surrounding the lower semiconductor chip. The dam structure includes narrow and wide dams disposed between the lower semiconductor chip and the bonding pads. The wide dam has a greater inner width than the narrow dam. The semiconductor packages further includes an underfill disposed inside the dam structure and being filled between the substrate and the lower semiconductor chip.

公开(公告)号：US20210407923A1

公开(公告)日：2021-12-30

申请号：US17167789

申请日：2021-02-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONGHO KIM ,  JONGBO SHIM ,  HWAN PIL PARK ,  CHOONGBIN YIM ,  JUNGWOO KIM

IPC: H01L23/538 ,  H01L23/13 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10

Abstract: A semiconductor package substrate includes a substrate having a bottom surface including a cavity structure defined therein. The cavity structure includes a floor surface. A passive device structure has at least a partial portion of the passive device structure disposed in the cavity structure. The passive device structure includes a first passive device and a second passive device that are each electrically connected to the floor surface of the cavity structure. At least partial portions of the first passive device and the second passive device vertically overlap each other.

公开(公告)号：US20220115281A1

公开(公告)日：2022-04-14

申请号：US17350329

申请日：2021-06-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JI HWANG KIM ,  DONGHO KIM ,  JIN-WOO PARK ,  JONGBO SHIM

IPC: H01L23/13 ,  H01L25/10 ,  H01L21/48 ,  H01L25/00

Abstract: A semiconductor package includes: a lower package: an upper substrate on the lower package: and connection members connecting the lower package to the upper substrate. wherein the lower package includes: a lower substrate; and a lower semiconductor chip, wherein the upper substrate includes: an upper substrate body: upper connection pads combined with the connection members: and auxiliary members extending from the upper substrate body toward the lower substrate, wherein the connection members are arranged in a first horizontal direction to form a first connection member column, wherein the auxiliary members are arranged in the first horizontal direction to form a first auxiliary member column, wherein the first connection member column and the first auxiliary member column are located between a side surface of the lower semiconductor chip and a side surface of the lower substrate, and the first auxiliary member column is spaced apart from the first connection member column.