公开(公告)号：US20250130268A1

公开(公告)日：2025-04-24

申请号：US18920172

申请日：2024-10-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Chunghyun KIM ,  Changsuk OH ,  Kiyoung JEON ,  Jaewon YOO ,  Myoungsuk JANG ,  Kwanghwa LEE ,  Seokjae HONG

IPC: G01R31/26 ,  H01L21/66

Abstract: A semiconductor test apparatus includes a base plate, side supporters provided as three or more on a lower surface of the base plate, an elastic cylinder and a side stopper provided on a lower surface of each of the side supporters, a center stopper provided laterally apart from the side supporters on the lower surface of the base plate, a stopper foot provided at one end of the center stopper, a foot supporter provided at one end of the stopper foot, a top plate disposed under the base plate to contact the elastic cylinder and the side stopper, the top plate including a center hole in a center portion thereof, and a substrate cover provided under the top plate, wherein the center stopper and the side stopper are selectively locked.

公开(公告)号：US20240319229A1

公开(公告)日：2024-09-26

申请号：US18606516

申请日：2024-03-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chunghyun KIM ,  Cheolkyu LIM ,  Byungwook JEONG

IPC: G01R1/067 ,  G01R1/073 ,  G01R31/28

CPC classification number: G01R1/06794 ,  G01R1/07342 ,  G01R31/2831

Abstract: A wafer testing apparatus includes a probe board disposed above a chamber, a wafer chuck disposed below the probe board and configured to support the wafer, a camera located between the probe board and the wafer chuck and configured to capture images of probe imaging points arranged on a lower surface of the probe board and wafer imaging points arranged on an upper surface of the wafer, and a controller electrically connected to the camera and configured to adjust a tilt of the probe board on the basis of image information acquired by the camera. The probe imaging points include a plurality of probe outer imaging points arranged in a rhombic pattern on the lower surface of the probe board, and the wafer imaging points include a plurality of wafer outer imaging points arranged in a rhombic pattern on the upper surface of the wafer.