Abstract:
A display device including: a panel unit including N data lines; and a data line driver unit including N channels, wherein the data line driver unit includes a channel amplifier unit, and a short detection device for detecting whether or not a short has occurred between two data lines among the N data lines, wherein N is an integer of 2 or more.
Abstract:
A display driver includes a first latch storing first image data, a second latch storing second image data, and a buffer unit including a plurality of output buffers outputting a source voltage corresponding to the first image data. Each of the plurality of output buffers includes an input stage, an output stage, and a pre-charge circuit connected between the input stage and the output stage. A pre-charge control unit compares the first image data with the second image data to control the pre-charge circuit.
Abstract:
A source driver including: a first source line; a second source line; a charge sharing switch which controls a connection between the first source line and the second source line; a first cross charge sharing switch which controls a connection between a first capacitor and the first source line, and a connection between a second capacitor and the second source line; and a second cross charge sharing switch which controls a connection between the first capacitor and the second source line, and a connection between the second capacitor and the first source line.
Abstract:
A source driver including: a first source line; a second source line; a charge sharing switch which controls a connection between the first source line and the second source line; a first cross charge sharing switch which controls a connection between a first capacitor and the first source line, and a connection between a second capacitor and the second source line; and a second cross charge sharing switch which controls a connection between the first capacitor and the second source line, and a connection between the second capacitor and the first source line.
Abstract:
An output buffer circuit includes an amplifier and a transmission circuit. The amplifier includes a plurality of inputs and an output. The inputs provide first input signals and second input signals to the amplifier. The output provides an output signal as a first input signal of the first input signals to the amplifier. The transmission circuit has an input coupled to the output of the amplifier and further has an output that provides a transmission circuit output signal as a second input signal of the second input signals to the amplifier.