公开(公告)号：US20140317471A1

公开(公告)日：2014-10-23

申请号：US14225725

申请日：2014-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-woo RYU ,  Chul-sung PARK ,  Tae-young OH ,  Chan-yong LEE ,  Tae-Seong JANG ,  Hoi-ju CHUNG ,  Gong-heum HAN

IPC: G06F11/10 ,  H03M13/13

CPC classification number: G06F11/10 ,  G06F11/1048 ,  H03M13/13

Abstract: A semiconductor memory device may comprise: at least one bank, each of the at least one bank including a plurality of memory cells; an error-correcting code (ECC) calculator configured to generate syndrome data for detecting an error bit from among parallel data bits read out from the plurality of memory cells of each of the at least one bank; an ECC corrector separated from the ECC calculator, the ECC corrector configured to correct the error bit from among the parallel data bits by using the syndrome data and configured to output error-corrected parallel data bits; and/or a data serializer configured to receive the error-corrected parallel data bits and configured to convert the error-corrected parallel data bits into serial data bits.

Abstract translation: 半导体存储器件可以包括：至少一个存储体，所述至少一个存储体中的每一个包括多个存储器单元; 纠错码（ECC）计算器，被配置为从从所述至少一个存储体中的每一个的所述多个存储器单元读出的并行数据位中生成用于检测错误位的校正子数据; 与ECC计算器分离的ECC校正器，ECC校正器被配置为通过使用校正子数据来校正并行数据位中的误差位，并且被配置为输出纠错的并行数据位; 和/或数据串行器，被配置为接收经纠错的并行数据位，并且被配置为将经纠错的并行数据位转换为串行数据位。

公开(公告)号：US20180190341A1

公开(公告)日：2018-07-05

申请号：US15830314

申请日：2017-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sung-geun DO ,  Jong-ho LEE ,  Chan-yong LEE ,  Min-soo JANG

IPC: G11C11/406 ,  G11C11/4063

CPC classification number: G11C11/40615 ,  G11C11/40618 ,  G11C11/4063 ,  G11C11/4074 ,  G11C2211/4067 ,  G11C2211/4068

Abstract: Provided is a memory device capable of reducing power consumption. The memory device includes a plurality of memory cells; and a self refresh controller configured to perform a refreshing cycle, which includes a first time interval and a second time interval, for a plurality of number of times, the second time interval being longer than the first section, wherein the self refresh controller is configured to perform a burst refreshing operation during the first time interval and to perform a power supply controlling operation during the second time interval.