公开(公告)号：US20240349484A1

公开(公告)日：2024-10-17

申请号：US18432290

申请日：2024-02-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taeyoung EOM ,  Hyungmin KO ,  Boryeon BAE

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/02 ,  H10B12/482 ,  H10B12/50

Abstract: A semiconductor memory device includes a substrate including a memory cell region, a first bit line on a center region of the memory cell region, a first landing pad on the first bit line, a first bit line capping pattern between the first bit line and first landing pad, a second bit line on an edge region of the memory cell region, a second landing pad on the second bit line, and a second bit line capping pattern between the second bit line and the second landing pad. The first and second bit line capping patterns vertically overlap the first and second landing pads, respectively. A distance from the top of the first bit line capping pattern from the top of the first landing pad is greater than a distance from the top of the second bit line capping pattern to from the top of the second landing pad.