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    Methods of manufacturing semiconductor devices
    2.
    发明授权
    Methods of manufacturing semiconductor devices 有权

    公开(公告)号：US11011526B2

    公开(公告)日：2021-05-18

    申请号：US16564688

    申请日：2019-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hye Sung Park ,  Jong Hyuk Park ,  Jin Woo Bae ,  Bo Un Yoon ,  Il Young Yoon ,  Bong Sik Choi

    IPC: H01L27/108 ,  H01L21/768 ,  H01L23/544 ,  H01L21/027

    Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

    Methods of manufacturing semiconductor devices
    3.
    发明授权
    Methods of manufacturing semiconductor devices 有权

    公开(公告)号：US11581318B2

    公开(公告)日：2023-02-14

    申请号：US17237195

    申请日：2021-04-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hye Sung Park ,  Jong Hyuk Park ,  Jin Woo Bae ,  Bo Un Yoon ,  Il Young Yoon ,  Bong Sik Choi

    IPC: H01L27/108 ,  H01L21/768 ,  H01L21/027 ,  H01L23/544

    Abstract: A method of manufacturing a semiconductor device includes forming a first pattern structure having a first opening and a second pattern structure having a second opening on a substrate, forming a gap fill layer in the second opening, forming fences and contact structures in the first opening, removing the gap fill layer in the second opening, forming an upper conductive layer to cover the first and second pattern structures, the fences, and the contact structures, forming a mask pattern based on a photolithography process using the second pattern structure covered by the upper conductive layer as an align mark, and etching the upper conductive layer using the mask pattern to form upper conductive patterns. A width of the second opening is larger than a width of a first opening. A thickness of the upper conductive layer is smaller than a depth of the second opening.

    Semiconductor device having plural dummy memory cells
    4.
    发明授权
    Semiconductor device having plural dummy memory cells 有权

    公开(公告)号：US10964751B2

    公开(公告)日：2021-03-30

    申请号：US16586140

    申请日：2019-09-27

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Hao Cui ,  Se Yun Park ,  Jong Hyuk Park ,  Bo Un Yoon ,  Il Young Yoon

    IPC: H01L27/24 ,  H01L45/00

    Abstract: A semiconductor device that includes a plurality of word lines disposed on a substrate in which p-type and n-type active regions are defined, and extends in a first direction. A plurality of bit lines is disposed on the plurality of word lines and extends in a second direction, perpendicular to the first direction. A plurality of memory cells is disposed between the plurality of word lines and the plurality of bit lines and each includes a data storage pattern. The plurality of memory cells includes a plurality of dummy memory cells and a plurality of main memory cells. An upper surface of the data storage pattern of the main memory cells is higher than an upper surface of the data storage pattern of the dummy memory cells.

    Semiconductor devices including insulating capping structures
    7.
    发明授权
    Semiconductor devices including insulating capping structures 有权

    公开(公告)号：US10403640B2

    公开(公告)日：2019-09-03

    申请号：US15933062

    申请日：2018-03-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang Sun Hwang ,  Ki Chul Park ,  Young Beom Pyon ,  Byoung Ho Kwon ,  Bo Un Yoon

    IPC: H01L27/115 ,  H01L27/11582 ,  H01L23/535 ,  H01L27/11573

    Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.

    SEMICONDUCTOR DEVICES INCLUDING INSULATING CAPPING STRUCTURES
    10.
    发明申请
    SEMICONDUCTOR DEVICES INCLUDING INSULATING CAPPING STRUCTURES 审中-公开

    公开(公告)号：US20190074289A1

    公开(公告)日：2019-03-07

    申请号：US15933062

    申请日：2018-03-22

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Chang Sun Hwang ,  Ki Chul Park ,  Young Beom Pyon ,  Byoung Ho Kwon ,  Bo Un Yoon

    IPC: H01L27/11582 ,  H01L23/535 ,  H01L27/11573

    CPC classification number: H01L27/11582 ,  H01L23/535 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11573 ,  H01L27/11575

    Abstract: A semiconductor device including an insulating capping structure is provided. The semiconductor device may include a plurality of gate electrodes vertically stacked on a substrate and an insulating capping structure on the plurality of gate electrodes. The insulating capping structure may include a first upper surface and a second upper surface. A first distance between the first upper surface and the substrate may be greater than a second distance between the second upper surface and the substrate. The first upper surface may not overly the second upper surface. The semiconductor device may include a memory cell vertical structure passing through the first upper surface, the plurality of gate electrodes, and the insulating capping structure. The memory cell vertical structure may be spaced apart from the second upper surface. The semiconductor device may include a bit line electrically connected to the memory cell vertical structure.

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