公开(公告)号：US20170062493A1

公开(公告)日：2017-03-02

申请号：US15068368

申请日：2016-03-11

Applicant: Samsung Display Co., Ltd.

Inventor： Young Jae JEON ,  Jae-Hyun PARK ,  Sang Ju LEE ,  Jae Ho CHOI ,  Hye Won HYEON

IPC: H01L27/12 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/1362 ,  G09G3/36 ,  G02F1/1335

CPC classification number: H01L27/1288 ,  G02F1/134363 ,  G02F1/136286 ,  H01L27/124

Abstract: The present inventive concept relates to a display device and a manufacturing method thereof. A display device according to an exemplary embodiment of the present inventive concept includes: a substrate; a first gate conductor provided on the substrate; and a gate insulator provided on the first gate conductors, wherein edges of the first gate conductor are recessed from edges of the first gate insulator, and the edges of the first gate insulator are respectively parallel with the edges of the first gate conductor.

Abstract translation: 本发明构思涉及显示装置及其制造方法。 根据本发明构思的示例性实施例的显示装置包括：基板; 设置在所述基板上的第一栅极导体; 以及栅极绝缘体，其设置在所述第一栅极导体上，其中所述第一栅极导体的边缘从所述第一栅极绝缘体的边缘凹陷，并且所述第一栅极绝缘体的边缘分别与所述第一栅极导体的边缘平行。

公开(公告)号：US20170357115A1

公开(公告)日：2017-12-14

申请号：US15412930

申请日：2017-01-23

Applicant: Samsung Display Co., Ltd

Inventor： Young Jae JEON ,  Il YOU ,  Seung Rae KIM ,  Chun Yan JIN ,  Beom Soo PARK ,  Jae Hyun PARK ,  Sang Ju LEE ,  Hye Won HYEON

IPC: G02F1/1368 ,  H01L29/417 ,  G02F1/1343 ,  H01L29/786 ,  H01L27/12 ,  G02F1/1362 ,  H01L29/423

CPC classification number: G02F1/1368 ,  G02F1/134309 ,  G02F1/136209 ,  G02F1/136227 ,  G02F1/136286 ,  G02F2001/134318 ,  G02F2001/136295 ,  H01L27/1248 ,  H01L29/41733 ,  H01L29/41775 ,  H01L29/42384 ,  H01L29/78636 ,  H01L29/78696 ,  H01L2029/42388

Abstract: A display device is provided. The display device includes a base; a gate conductor disposed directly on the base and including a gate line and a gate electrode; a gate insulating layer disposed on the gate conductor and including an overlap portion, which overlaps with the gate conductor, and a non-overlap portion, which is connected to the overlap portion, does not overlap with the gate conductor, and is spaced apart from the base; and a semiconductor pattern disposed on the gate insulating layer and overlapping with the gate electrode, wherein edges of the gate insulating layer project further than edges of the gate conductor and edges of the semiconductor pattern.